I have MAX V CPLD there is a problem with the I/O pins when I assign Signal on the I/O some of these I/O fails to out put the signal correctly.
for example, I wrote a dummy Verilog design to set all the output pins to High for 3 seconds then low for 3 seconds when I observe the output value on the I/O pins some of the pins doesn't work correctly (always low).
Well, you have to be a LOT more forthcoming with all the information about your design and environment. Like:
Exactly which CPLD. Full part number.
Exactly which version of Quartus. And your O/S environment helps too.
Development board or your own design?
Show your verilog.
What are the I/O types of the configured I/Os? Show your .qsf file setup for the relevant pins. Or screenshot of Quartus pin setup.
Lots of smart people here willing to help, but unfortunately I don't think any are mind readers.
We are using MAX v (5M1270ZT144A5) CPLD on Quartus Prime 20.1 on Windows 11 we Designed our own PCB and used this board for several times and it was working correctly until we recognize some weird behaver we checked the I/O pins we found that they aren't working correctly for example we drive high on one of the input pins we traced this signals from the pin header on the PCB until the actual pin on the CPLD (the IC leg) and the High signal reach the CPLD correctly but when we try to monitor this signal inside the CPLD using (in system source and probes) the signal isn't reached correctly.
this is our pin assignment
Some of these Pins working correctly the pins that are not working Pin (7,24,39,48,52,63)
Can you share your simple design so I can test with our devkit?
Most of the time, the root cause could be the pin assignment where you assigned a specific pin, but the VCCIO of that pin does not matched with the real VCCIO on board.