FPGA, SoC, And CPLD Boards And Kits
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Max V CPLD Development Kit


FPGA, SoC, and CPLD Boards and Kits Forum,

I am new to CPLDs and for almost a month I've been seeking help from Intel and Forum with no responds. My second original post was applied in the New User Forum and link is provided below. Also, the second original has some images attached. I seriously need help. Thank you.


MAX V CPLD Development Kit - Will not work for a simple logic circuit

by Moe1 in FPGA, SoC, And CPLD Boards And Kits

07-03-2021 05:28 PM
Intel Community, I recently purchased the Max V Development Kit. I figured out how to use the Quartus Prime Lite and successfully installed the Blaster. Created a simple encoder logic circuit, two inputs, one as a 0 or 1 input and the other an enable input. The circuit comprises of two 'AND' gates and on 'NOT' gate. When the first input is low the first AND gate input is low and the other AND input is high because of the NOT gate. The second input is an enabling input which allow the true states of the AND gates to be outputted else the outputs are always low when the enable input is low. Successfully created this logic, manually assigned pins, compiled and synthesized, etc. Successfully downloaded to the Max V kit. Wired up to test the CPLD, nothing. Absolutely nothing. I am not sure how to wire the board for the inputs to be applied. I assigned J6.1 as input, J6.2 as enable input. Pins J6.9 and J6.10 are the two AND gate outputs. Also, I accepted the 3.3 LV default. When I test with external switches to the board and outputs to a O-scope, nothing. I have searched for weeks any examples on interfacing external inputs devices and output devices to the board and have not found any thing. Is there any help to be found in the Intel Community? Thank you. My email is : moejjunior@gmail.com Please note that I originally posted this last month with no reply. Frustrating.

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Honored Contributor III

I replied to you in your last post.  You're using the wrong pins for the outputs on that board.



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