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when I run the Modelsim[starter edition 10.6d] to simulation my Verilog code, there are many error, I already have tried many ways, but it's failure
do anybody know it?
Could you check the below solutions?
please let me know, how it works for you.
May I know any update?
Over time, I will update, thanks
Have you resolved the issue?
May I know any update or Should I consider that case to be closed?
Yes， I have already resolved it use the methods above,
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