Hi all.Few months (maybe a couple of years) ago I was used to post a lot into this forum. My question were inherent video IPs, and my task was to use them ino a pipeline to be implemented into a DE2 board and, later, on a cyclon3 evm ep3c120. Now, I decided that it would be nice if I would share my work with you. Be aware that for the ep3c etcetc they are based on Altera's example. Also, I wrote many bloks from verilog code I wrote but they are NOT optimized or similars. Furthermore, Other people I know worked on that and debugged many conceptual errors. The projects I am sharing are an histogram equalization for DE2, a retinex using fir filters (Higpass and lowpass in oreder to extrac illuminance an reflectance) and finally a work based on an article from two Ph.D I met at university, " A flexible FPGA architecture for illuminance-reflectance video enhancement" by Stefano Marsi, Ph.D Giovanni Ramponi, Prof. , published on "Journal of Real-Time Image Processing". They're based on Y channel only, so there is no compensation for the subsampled CbCr channels. You are free to use the three projects, but a) they are provided "as they are" b) I have no responsability if you break your evm, fpga, pc, etc using the sources I provide. c) I provide them for study. Do not use them for commercial purposes. Or If you use them, I will not take any responsability if there are faults, people dies or something like that. d) If you use them for academic or other tasks, please, cite me in your work, at least in bibliography. PM me and I will send you my data. Maybe I can also explain obscure portions of code. e) almost all projects are based on vip_example_design_3c120_v91_revB. Right now, both the *.quar are heavyer than the attchment policy permits me to upload. I'll try to upload them on external sites (like filesharing or similars ) . And I ca'nt find my old project for DE2. I'll search for it an will upload also that. If you are interested I mean :D Greetings, Phate Article-based retinex http://www.sendspace.com/file/ddytj2 a "newer version", close to the final one: http://www.sendspace.com/file/plkm5i FIR based-retinex http://www.sendspace.com/file/5bhdle A little bit detail: the video processing is hardware based. Nios fills the LUTs and, where possible, reads average luminance for one or more frames, then performs processing and refreshes LUTs. Many VIps are configured runtime by nios.
--- Quote Start --- Hi Phate, The links are no good anymore. could you please post a working download links ? Thank you so much. --- Quote End --- Mmmh It's been awhile since I posted those links. I'll try to search in my "storage room" if I can find the projects, but I can't guarantee I'll find them.
--- Quote Start --- Mmmh It's been awhile since I posted those links. I'll try to search in my "storage room" if I can find the projects, but I can't guarantee I'll find them. --- Quote End --- Hi! I need help! now writing an article about the different types of local contrast enhancement and trying to implement different techniques in FPGA, please help , really need your work to not repeat mistakes and do not plagiarism and do not do what is already implemented and ready to ask ,