Nios II and ADC -- Cyclone III Dev. Board

[Altera_Forum]

Sorry, I've only just started using Altera FPGAs, and so far things went fine with Verilog and without using Nios II.  

 I would now like to use a Nios II soft-processor for some signal processing applications (matched filtering, for example). I would like to read the incoming signal from the ADC.   I found a few examples on how to use the Nios II, but I did not find a single example, where an ADC or DAC were used. Where can I find such? How can I access the data that is coming from the DAC?   Is it best to write the data from the DAC into some memory (SRAM, DDR) and then access that memory from Nios II?   I'm a beginner with this and confused...   Any help is appreciated! thanks in advance.

[Altera_Forum]

You could write a verilog block that reads the ADC and make it into a custom component for SOPC. That way your sample block could be connected to NIOS via the avalon bus. 

 http://www.altera.com/literature/hb/qts/qts_qii54004.pdf  If you like you can use a dma controller to write the data directly from your sample block to the SDRAM if you like, that could be useful if you sample at a high rate.  Best Regards, Ola Bångdahl

[Altera_Forum]

Thank you for your reply, Bango! I will try to study the link that you have provided.  

 But are there really no examples from Altera where ADC and DAC are being used with the Nios II?  The "first steps" with Altera FPGA's are good, but I somehow miss the "second step" examples...   Furthermore, is there an example explaining the usage of the dot-matrix LCD from within NiosII or directly through VerilogHDL?   Thanks for all your help!

[Altera_Forum]

Usually ADCs and DACs have some sort of communication interface like SPI or I2C, which you will be able to find ready made avalon components for. If you don't find anything you will need to implement the actual sampling logic yourself and just attach an avalon slave port to your block. The last part is similar to all avalon slaves and can be deduced from the exampels. 

 I'm no expert on displays so I'll let someone else handle that. If you post a link to the datasheet it might be easier to help.  //Ola

[Altera_Forum]

There is a nice selection of HSMC compatible ADC/DAC daughter cards available to connect to the Cyclone III Dev Board. 

 Check out the following listing: http://www.altera.com/products/devices/cyclone3/design/cy3-devkits.html#table2   Aloha - Tom

[Altera_Forum]

Thank you to Hawaii! I actually have an HSMC ADC card, the one that comes with the DSP Development board, but there are no examples where sampled data is written from the DAC to the SDRAM.  

 What I would like to do:  1) I would like to generate a signal on the FPGA and send it to the DAC (this part works fine).  2) I would like to sample the incoming signal and write the data (about 50MB) into the SDRAM 3) I would like to read the contents of the SDRAM into the NIOS2 Processor (inside the same CycloneIII FPGA) and do some signal processing operations on the sampled data.   I managed to generate the signal and output it through the DAC and  sample the incoming signal with the ADC. I can also read to and write from the SDRAM from the Nios Processor SOPC; I do this with a DDR2 SDRAM HP Controller (as described in AN517).   My questions are as follows: How can I write the data from the ADC to the SDRAM, so that I can access it again from within the Nios2? Do I need two controllers for that, one for the Nios2 Interface, and one to interface with the ADC? How do I best interface the "signal generation block" with the NIOS2?   The interface of the ADC is a 14 bit parallel output, a clock and an output-enable.   The questions here are probably naive or stupid, but it's my first design... apologies. And I just wonder how people start using FPGAs - the first steps were easy, but I cannot find a lot of documentation for "second steps"...   thanks in advance for any kind of help!   mfrey

[Altera_Forum]

I want to make sure I understand the problem correctly. 

You have samples and you need to write these samples into SDRAM using Verilog not the NIOS.  I know that NIOS can write into SDRAM. So, you can pass these signals from Quartus to NIOS using SOPC. Then NIOS can do the writing for you.  However, NIOS reading rate is slow and varying. So, the sampling accuracy will be bad.   So, I recomend to sample and write into SDRAM using Verilog Quartus. Then NIOS can read from SDRAM to do your signal processing.  The question now is how Verilog do the wrting into SDRAM??? Actually, I still search about it. So, lets work in this issue together. OK

[Altera_Forum]

I would like to sample at 100-150MHz @ 14bits, so sampling through the Nios does not seem like an option. I might need DMA for high speed.  

I'm still confused about SOPC Builder, how to bring parts together. And I'm also confused how to connect the ADC with the SDRAM... Verilog or with Block Diagrams should be possible.   Thanks for any help!

[Altera_Forum]

There is a reference project provided by Altera in the following link: 

http://www.altera.com/support/refdesigns/sys-sol/indust_mil/ref-adi-sdram.html  I am still trying it.  Good Luck.  Keep me updated.

[Altera_Forum]

Hey, what did you find? Did you check the link I provided before?

[Altera_Forum]

Sorry for the late reply... but the link didn't bring me much further. Thanks anyway. What I'm doing now is looking at the example driver given in  

"DDR and DDR2 SDRAM High-Performance Controller User Guide"  http://www.altera.com/literature/ug/ug_ddr_ddr2_sdram_hp.pdf  I think this can be changed and used for my purpose.   Thanks for all help!

[Altera_Forum]

Hey, what did you find? 

i have the same pblm , i have to use ADC and DAC with the Nios II and write into SRAM using vhdl !!!! how can i do that and communicate DAC to NIOS II also ?