Hi all, i have a question.What is the total memory size from the DE0-Nano Board? In the tutorials they always use 26000bytest but is that all?? I use the SOPC Builder. My problem is for the normal c library the memory is to small.So i must use the smaller one. But I want use the normal library. Or is it better to use the 32Mb SDRAM?? If the SDRAM difficult to use because I`m a beginner?? Sorry when the English is not so good but I´m tiered and it´s late in Germany ;) thx I hope someone can help me.
I'm not sure how much memory that device has, Quartus II will tell you and so will the device documentation. If you must run with the full C library then I recommend adding the SDRAM controller to the design. It would probably easier to take a design that already has the SDRAM controller and just remove the stuff you don't need. I'm not overly familar with that board but I'm sure there are plently of designs you can compile with open core plus JTAG tethering.
I agree with Bad Omen. The internal memory in the DE4-nano FPGA is 594 kbits. So the maximum usable TCM memory would be around 64 K bytes if you are lucky.If you want to use the full C library, I would recommend starting from the Terasic Nios example that has the SDRAM controller in it. then going from there. Pete
Sounds good, but i searched for an example with SDRAM where I can find it? I searched but I only find this pdf. http://people.ece.cornell.edu/land/courses/ece5760/de2/tut_de2_sdram_verilog.pdf That is for the DE2 not for th DE0 but the way looks the same.