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Hello!
I am following https://ofs.github.io/ofs-2024.2-1/hw/common/user_guides/oneapi_asp/ug_oneapi_asp/ to set up OneAPI for the Agilex 7 I-Series Development Kit (2x R-Tile, 1x F-Tile).
At step 2.5.1 Compile Initialization Bitstreams the command
./build-default-binaries.sh -b ofs_iseries-dk
failed with the output in the attached file.
Regarding the Verilog error, I found this https://www.intel.in/content/www/in/en/programmable/quartushelp/22.1/index.htm#msgs/msgs/evrfx2_veri_opposite_direction.htm. Is there actually an error in ofs_plat_prim_burstcount1_mapping_gearbox.sv or am I doing something wrong?
All tools should be the versions mentioned in the OneAPI ASP Getting Started Guide but the host OS is Ubuntu 24.04.
I would appreciate some help. Thanks!
Felix
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Hi @gustifix2,
Thank you for posting in Intel community forum and hope all is well.
Noted on the issues faced with the details explanation, please do provide us some time to check issues mention.
Will get back to you as soon as possible.
Appreciate the patients.
Best Wishes
BB
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Hi @gustifix2,
Appreciate the patients, after some discussion and alignment it seems that the oneAPI OFS design example required specific RAM configuration which is 2x8GB, hence after some OFS configuration setup with the right RAM configuration setting, the oneAPI kernel compilation would be successfully.
Hope that clarify, please do let us know if there is further doubts.
Best Wishes
BB
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Hi @gustifix2,
Greetings, just checking in to see if there is any further doubts in regards to this matter.
Hope your doubts have been clarified.
Best Wishes
BB
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Hi @BoonBengT_Intel ,
Thank you for the response! I haven't had time to try your solution yet, but when I get to it, I will post here to let you know if it worked.
Best regards
Felix
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Hi @gustifix2,
Sure thanks for the updates, hence while waiting for future updates, it will be transitioned to community support for further help on doubts in this thread. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
Thank you for the questions and as always pleasure having you here.
Best Wishes
BB
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Hi @BoonBengT_Intel ,
Could you point me to some documentation for what exactly should be changed? I assume I have to change the memory configuration of the FIM, similar to 4.7 Modify the Memory Sub-system. I tried removing the 2 DDR4 interfaces with location "North I/O Row" in the picture below:
I assume the "North I/O Row" is connected to the two DIMM slots and "South I/O Row" to the 2x8GB soldered to the board based on this picture:
However, with just two "south" interfaces and after removing unused signals in the "Interface Requirements" window, I get a compilation error in build_top.sh script about the fitter not being able to place pins. It looks like I also have to adjust the pin constraints and remove the now unused pins. However, I'm not sure if this is even the right approach to change the RAM configuration to 2x8GB, so I wanted to ask here again first.
Also, I will be on vacation for two weeks and continue to work on this afterwards.
Thanks and best wishes!
Felix
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Hi @BoonBengT_Intel,
We are looking into the following up enquiries and will get back to you as soon as possible.
Please do expect some delay due to the holiday season.
Thank you for the patients
Best Wishes
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Hi @gustifix2,
Thank you for waiting and the patients.
After discussing this internally with our IP team, since the error are mentioning the fitter problem and we have unused pin. Hence we should remove them with the correct pin constraint.
It should work per the example design which requires 2x8gb external memory.
Hope that clarify.
Best Wishes
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Hi @gustifix2,
Greetings, just checking in to see if there is any further doubts in regards to this matter.
Hope your doubts have been clarified.
Best Wishes
BB
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Hi @BoonBengT_Intel,
After removing the 2 "North I/O Row" interfaces as described previously and removing all _mem[2] and _mem[3] constraints from syn/board/iseries-dk/setup/emif_loc.tcl, the FIM compile succeeded without timing violations after a few tries with different seeds.
However, after repeating the steps with OPAE_PLATFORM_ROOT now pointing to this new FIM build's pr_build_template directory, I got the same error (attached txt file) as in the beginning at step 2.5.1 Compile Initialization Bitstreams.
Best wishes!
Felix
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Hi @gustifix2,
Noted on the error details, seems to be some error during the FIM compilation.
Could you double confirm if it is 1 PF 1 VF configuration?
Will also suggest to check on the OPAE_PLATFORM_ROOT environment variable setting is pointing to the pr_build_template directory, and perhaps start from a clean oneapi-asp cloned repo.
Would also suggest to use the following command for the FIM compilation:
- Slim FIM with 2 PCIe Gen5x8 links, each with 1PF and 1VF, no HSSI:
$ ./ofs-common/scripts/common/syn/build_top.sh -p --ofss tools/ofss_config/pcie/pcie_host_2link_1pf_1vf.ofss iseries-dk:no_hssi,pr_floorplan=syn/board/iseries-dk/setup/pr_assignments_slim.tcl work_iseries-dk_slim
Hope that clarify
Best Wishes
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Hi @BoonBengT_Intel,
Thank you for all the help so far! With the new build_top.sh command the compile succeeded.
I continued the guide until section 2.5.3, where aocl diagnose succeeds but aocl diagnose acl0 fails. I attached the output of both commands.
I will try compiling the original FIM without my modifications to the DDR config again but use the new build_top.sh command and report back if it changes anything.
Best wishes
Felix
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OK, I tried it again with the unmodified FIM and got the same error from aocl diagnose acl0.
I also tried continuing the guide and built the board_test.fpga binary. It results in a similar error (attached file).
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I also tried running the simple-add and vector-add from oneAPI-samples, but they just show
Running on device: ofs_iseries-dk : Intel OFS Platform (ofs_ea00000)
Vector size: 10000
and nothing happens afterwards.
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Hi @gustifix2,
The error seems weird and it seems to be coming from the board test sample which are checking on FPGA board interface in this case the host and fpga. Suspect it maybe be a hardware issues/hardware configuration issues. May not be related to oneAPI setup. Hence would suggest to run the board test sample separately just to narrow down the issues, the repo are as below:
Perhaps it will also be good to validate the Agilex7 with the BTS. More details of the board test system can be found in the link below:
- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html (at the Table 3. Documentation)
Hope that clarify.
Best Wishes
BB
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Hi @BoonBengT_Intel,
For the board_test sample only 3 of the 7 tests pass, 2 (kernel clock frequency), 4 (kernel latency measurement), and 7 (unified shared memory bandwidth). I attached the full output.
Edit: I just saw that test 7 is actually skipped because the board does not support USM, so only 2 and 4 passed.
I also noticed the following error that continually appears in dmesg:
[ +0.000126] pcieport 0000:00:01.0: AER: Correctable error message received from 0000:00:01.0
[ +0.000002] pcieport 0000:00:01.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Receiver ID)
[ +0.000001] pcieport 0000:00:01.0: device [8086:a70d] error status/mask=00000001/00002000
[ +0.000000] pcieport 0000:00:01.0: [ 0] RxErr (First)
The BTS looks fine. I attached pictures of the 3 memory tests as examples.
Thanks and best wishes!
Felix
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Hi @gustifix2,
Thank you for the patients, noted on the result and we are consult the relevant team to get their inputs on this.
Please do give us some time as it may take a while due to the holiday season.
Best Wishes
BB
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Hi @BoonBengT_Intel,
No worries, thanks! I'll try some debugging in the meantime. I saw that a prebuilt FIM is available at https://github.com/OFS/ofs-agx7-pcie-attach/releases/tag/ofs-2024.2-1, so I'll follow the guide again using this FIM. If this doesn't change anything, I will also investigate the error in the board_test sample more. Maybe I can find out where in the stack the problem occurs.
Best wishes!
Felix
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Hi @BoonBengT_Intel,
I just created a new post because the current issue isn't really related to the original one I created this post for anymore: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/OneAPI-for-Agilex-7-I-Series-Dev-Kit-aocl-diagnose-acl0-and/m-p/1663345#M29250
Best wishes!
Felix

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