OpenCL 19.3 SD Card image for Intel Arria 10 Development Kit

[CJohn56]

Hi,

I am having problems with creating my own SD Card image for the Intel Arria 10 Development Kit.

I have tried the GSRD 19.1, but I cannot get the OpenCL Driver working.

I have also tried generating the device tree blob, compiling Linux, compiling u-boot, compiling the OpenCL driver approach, without luck.

Is there a pre compiled OpenCL driver or precompiled SD Card image for 19.1/19.3? I've noticed that there is an image in the 17.1 SDK, and there should be one for the 18.1 SDK (https://forums.intel.com/s/question/0D50P00004KyuxESAR/getting-started-with-the-intel-fpga-sdk-for-opencl-pro-edition-for-linux), but I can't seem to find one for 19.1.

[CJohn56]

Hi,

It looks like the driver compiles without any warnings or errors!

I have renewed our quartus license. However, when I try to compile the modified design, I get an error. I have tried to open the board.qsys and I get the same error there:

Error: DMA_system.fpga_to_sdram_dma.mm_read: mm_dma_read.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff) Error: DMA_system.fpga_to_sdram_dma.mm_write: mm_dma_write.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff) Error: qsys-generate failed with exit code 3: 2 Errors, 1 Warning Error: DMA_system.fpga_to_sdram_dma.mm_read: mm_dma_read.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff) Error: DMA_system.fpga_to_sdram_dma.mm_write: mm_dma_write.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff) Error: qsys-generate failed with exit code 3: 2 Errors, 1 Warning

This happens when I:

1. Copy the example project 'vector_add'
2. cd into the project
3. cd into device/
4. Run the base compile: 'aoc -bsp-flow=base vector_add.cl'
5. cd vector_add/
6. copy the BSP from $INTELFPGAOCLSDKROOT/board/a10soc/hardware/a10soc_2ddr/* to .
7. open the project top.qpf in quartus
8. open the board.qsys file, which opens platform designer
9. Upgrade all the IPs to 19.1 or 19.3 (only some are 19.3)
10. Rename the 'Hard Processor System Intel Arria10 FPGA IP' from 'arria10_hps' to 'a10_hps'
11. Save
12. Run 'Sync System Infos'
13. Run 'Validate System Integrity'
14. Run 'Generate HDL'

Then I get the errors. Even though some of the HDL files are generated, Quartus fails to compile during the 'IP Generation' step

[MEIYAN_L_Intel]

Hi, 

From the error message, your DMA_system.fpga_to_sdram_dma.mm_read address width is 32 bits while avalon slave which you trying to connect your master requires 33 bits.

You may need to increase the address width for DMA system by double click the DMA_system.fpga_to_sdram_dma.mm_read component to see whether it is possible to increase its address width. 

Thanks

[CJohn56]

Hi,

I've succesfully changed the width of the DMA, by opening 'DMA_system.qsys' and upgrading all of the IPs to 19.1. Then I changed the parameters of the 'Modular Scatter-Gather DMA Intel FPGA IP' called 'fpga_to_sdram_dma', by ticking the box 'Use pre-determined master address width' and by entering '34' into the 'Pre-determined master address width'.

Then I went into all of the remaining '.qsys' files, and upgraded their IPs to 19.1. Then I was able to sync, validate and generate all of the qsys files. Quartus still fails however, in the 'Analysis and Synthesis' step of the 'opencl_bsp_ip'. I have attached the messages I get from Quartus.

[MEIYAN_L_Intel]

Hi,

From the quartus_messages file, I saw there are some ports could not be found.

I would like to know do you used the HLS flow to add opencl into platform designer?

May I have the flow from beginning still now?

Also, can I have the full design file to duplicate the problem in order to further investigate the problem?

Thanks

[CJohn56]

Hi,

I have used the flow from the base revision compile as stated in the manuals. I can reproduce with the following steps on an Ubuntu 18.04 with the Intel OpenCL for FPGA version 19.3:

source $INTELFPGAOCLSDKROOT/init_opencl.sh cp -r $INTELFPGAOCLSDKROOT/examples_aoc/vector_add/ . cd vector_add/device/ aoc -bsp-flow=base vector_add.cl cd vector_add/ cp -r $INTELFPGAOCLSDKROOT/board/a10soc/hardware/a10soc_2ddr/* . $INTELFPGAOCLSDKROOT/../qsys/bin/qsys-edit acl_kernel_interface_soc_pr.qsys --quartus-project=top.qpf $INTELFPGAOCLSDKROOT/../qsys/bin/qsys-edit ddr4.qsys --quartus-project=top.qpf $INTELFPGAOCLSDKROOT/../qsys/bin/qsys-edit dual_port_splitter.qsys --quartus-project=top.qpf $INTELFPGAOCLSDKROOT/../qsys/bin/qsys-edit kernel_mem.qsys --quartus-project=top.qpf $INTELFPGAOCLSDKROOT/../qsys/bin/qsys-edit mem.qsys --quartus-project=top.qpf $INTELFPGAOCLSDKROOT/../qsys/bin/qsys-edit DMA_system.qsys --quartus-project=top.qpf $INTELFPGAOCLSDKROOT/../qsys/bin/qsys-edit board.qsys --quartus-project=top.qpf quartus --64bit top.qpf

For each of the .qsys files, I have updated all of the IPs to the newest version, which is either 19.1 or 19.3, synced all the system infos, validated the system integrity and generated HDL.

Furthermore, I have renamed the name of the 'Arria 10 HPS IP' from 'arria10_hps' to 'a10_hps'. Finally, I've changed the bitwidth of the fpga_to_sdram_dma in DMA_system.qsys from automatic to 37 bits.

In Quartus, I just hit 'Start compile' as stated in the guide.

I have zipped and attached the folder 'device/' folder.

[MEIYAN_L_Intel]

Hi,

I would like to know which manual you have follow? Can you give me the link for the manual you have follow?

Also, I would like to know do you have modify any thing in the process? If yes, can you explain which part you have modify? This is because I need to look into it for further investigate the problem.

Also, if you have do the modification, can you send me the full design before modification? This is because I would like to compare both design before modification and after modification.

Thanks

[CJohn56]

Hi,

I have followed the guides you have linked to. Primarily https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug-aocl-a10socdk-platform.pdf

The only modifications I have made are the steps specified in my previous posts.

I have attached the base revision compile before modification, and the BSP before modification (which is a10_soc.zip inside vector_add.clean.zip).

[MEIYAN_L_Intel]

Hi,

I am still looking into the error and comparing changes that had been done.

Thanks

[MEIYAN_L_Intel]

Hi,

I had reviewed your file with kernel memory ip and the error show the kernel memory port cannot be found. Then, you may need to look at the files from hierarchy OpenCL compilation in order to solve the problem.

Thanks

[CJohn56]

Hi,

I have tried to compile in Quartus from the opencl_bsp_ip. Is this what you mean? Is there a guide you can point me to?

[MEIYAN_L_Intel]

Hi,

There are some port cannot be recognize in the pr_region.v file. You many need to refer the link below to solve the error:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/evrfx2_veri_cant_find_port.htm

Thanks

[CJohn56]

Hi,

These files are files generated by Intel tools and are related to Intel IPs. Should I be editing them? Shouldn't the Intel tools generate correct code?

Regardless, yes I can see that the kernel_system file only has one set of memory ports, where the instantiation of it in pr_region.v tries to assign it two sets of memory ports. Is this then due to it using a wrong IP core, or is it the qsys, which generates something wrong?

[MEIYAN_L_Intel]

Hi,

Since kernel _system file is only one set memory ports while your instantiation have two memory port, this cause the problem. This issue might come from the hierarchy opencl compilation file which you may look into it. You have to instantiate the port correctly.

Thanks