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Altera_Forum
Honored Contributor I
825 Views

PIN Assignment for Embedded Evaluation Kit (NEEK), Cyclone III

Hi ... 

I am using Quartus II and qsys for NEEK. My system in qsys basically has a NIOS II processor, SDRAM, Triple speed ethernet and LEDs. I want to know how do I assign the pins. I was trying to look into documents to find csv file, but there is no such thing for NEEK. Where can I get the csv file for NEEK? How does the "Import assignment" work - where can I find the .qsf file?  

Thanks.
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4 Replies
Altera_Forum
Honored Contributor I
45 Views

i have same problem too. 

is there any docs for beginner ?
Altera_Forum
Honored Contributor I
45 Views

The FPGA board in the NEEK is a Cyclone III starter board. 

http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html 

 

What you need should be in it's documentation. 

 

Or, you can also take it from these example projects: 

http://www.altera.com/literature/an/an521_design_example.zip
Altera_Forum
Honored Contributor I
45 Views

Thanks for the documents. All I was concerned is, for NEEK Cyclone III starter board how to assign pins? 

 

They have an option of importing pins (.qsf) file. But wer do I get that from? 

Or For manual Pin assignment is there any datasheet for that.? 

 

I am so confused with this pin assignment:(. How does it works?
Altera_Forum
Honored Contributor I
45 Views

Well, usually you'd write a top level module that declares the I/O signals you need in your design, compile it, open the Pin Assignment editor and start assigning signals to pins. 

 

To know which pins to assign your signals to and which I/O standard to use, you need to read the board's schematics and/or documentation. 

 

In this case, it's the board's Reference Manual. 

For example, the Reference Manual say's that there's a 50 MHz clock signal connected to FPGA pins B9 and V9, using 2.5V I/O. 

So, if I want to use a 50 MHz clock signal named "clk" in my design, I need to assign "clk" to pin B9 or V9 and select the 2.5V I/O standard, using the Pin Assignment editor. 

 

However, in that board's documentation, there's an example project where all the signals that are connected to the FPGA have already been declared and assigned. 

You'll find it in examples/cycloneIII_3c25_start_golden_top
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