PLL relocation in CycloneV

[manishkumar]

Unable to relocate the PLL in in CycloneV Device 5CEBA5U19C7.
Tried with Assignment Editor options.

Getting errors:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic fractional PLL that is part of PLL Intel FPGA IP pll_adc_mclk in region (68, 53) to (68, 60), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The fractional PLL name(s): pll_adc_mclk:pll_adc_mclk_inst0|pll_adc_mclk_0002:pll_adc_mclk_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (177020): The PLL reference clock was not placed in a dedicated input pin that can reach the fractional PLL
Info (175026): Source: pin ip_adc_clk
Info (175015): The I/O pad ip_adc_clk is constrained to the location PIN_M16 due to: User Location Constraints (PIN_M16)
Info (14709): The constrained I/O pad is contained within this pin
Info (175029): 1 location affected
Info (175029): FRACTIONALPLL_X68_Y54_N0
Info (175015): The fractional PLL pll_adc_mclk:pll_adc_mclk_inst0|pll_adc_mclk_0002:pll_adc_mclk_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL is constrained to the location FRACTIONALPLL_X68_Y54_N0 due to: User Location Constraints (FRACTIONALPLL_X68_Y54_N0)

[AqidAyman_Intel]

I found a Knowledge Base article mentioned:

This error can occur in Stratix® V, Arria® V, and Cyclone® V devices when the PLL Intel® FPGA IP is sourced by a global or regional network where that network is driven by a dedicated clock input pin. The connection of a dedicated clock pin to a phase-locked loop (PLL) over a global / regional network is legal, however, the Quartus® II software will not allow this connection without an explicit promotion of the clock to the global or regional resource through a clock control block.

Resolution

Insert an ALTCLKCTRL Intel® FPGA IP in the clock path between the dedicated clock input pin and the PLL Intel FPGA IP. Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL Intel® FPGA IP must be instantiated in your design.

This is not necessary when the clock input pin has dedicated access to the PLL Intel FPGA IP. 

Can you help to try the resolution suggested?