Pin assignment De-1 SoC board

[Altera_Forum]

Hi Altera forum, 

 I was trying to use certain pins on my dev board, but Quartus tells me it cant assign the 25MHz clock and DDR3 pins "they are reserved for the programmer pins". Which is bogus I guess. Is there a workaround to this problem?

[Altera_Forum]

So ill answer my own post then, A thing that does compile is the golden top, does mean I have to move the entire project to there `or ignore Quartus features like the pin planner and assignment editor` In which I used the pin planner extensively.. So lets do that..

[Altera_Forum]

Ofcourse it was foolish of me to believe that would solve my troubles. The thing is it's connected to the DDR3 ram module on the board and I can only guess it needs an on chip termination IP.  

Must be the soul reason the pins aren't planned in the golden top module. But at the frequencies im running it at it's no different from the other stuff im running it at.. So are there any workarounds to this issue?

[Altera_Forum]

I used the assignment editor to give it 85 Ohms of OCT, it compiled but no luck. Any help would be greatly appreciated.. Cant possibly mean I have to dedicate an entire GPIO header to this issue?  

    Error (14566): Could not place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s))  Error (175020): Illegal constraint of pin to the region (89, 69) to (89, 80): no valid locations in region  Info (14596): Information about the failing component:  Info (175028): The pin name: WE  Info (14597): No legal location could be found for this component out of 1 considered location(s). Reasons why each location could not be used are summarized below:  Error (184016): There were not enough single-ended output pin locations available (1 location affected)  Info (175029): C28  Info (175015): The I/O pad WE is constrained to the location PIN_C28 due to: User Location Constraints (PIN_C28)  Info (14709): The constrained I/O pad is contained within this pin