Power Sequence of Arria V GX (FPGA)

[NM11]

We are using Arria V GX (FPGA) in a prototype we are considering developing.
I have 3 technical questions about Power Sequence.

1.

In the Arria V Device Datasheet, at the end of Table 3 of 1.1.1.3.1, Recommended Operating Conditions, there is a statement that "the maximum power supply ramp time is 100ms".
What is the effect if this is exceeded?
In our test, the maximum ramp time is about 200ms. If necessary, we can show you the waveforms measured with an oscilloscope.
Our prototype seems to be working fine so far.

2.

In the Arria V Device Datasheet, at the beginning of Table 3 of 1.1.1.3.1, Recommended Operating Conditions, it is stated that "Power supply ramps must all be strictly monotonic, without plateaus".
How monotonic must these ramps be?
In our tests, some pins do not appear to be monotonic. If necessary, we can show you the waveforms obtained with an oscilloscope.

3.

What are the consequences of not meeting these monotonicity requirements in #2?
Our prototype seems to be working fine so far.

[lixy]

Hi,

About your first question about ramp time, here's my answer.

A POR event occurs when you power up the Intel Arria V device until all power supplies monitored by the POR circuitry reach the recommended operating range within the maximum power supply ramp time, tRAMP.

As you can see from the Figure 11-7 in the Arria V handbook, POR delay and Configuration time will follow the tRAMP. If tRAMP is not met, the I/O pins and programming registers remain tri-stated, which may cause device configuration to fail.

I will check your second question and see if I can give an answer.

Thanks & Regards,

Xiaoyan

[NM11]

Hi Xiaoyan-san,

Thank you for your answer.

Best Regards,

Naoki

[lixy]

Hi Noaki,

Maybe you can show me the power waveform for your second question?

It is hard to say how it will affect the device if power doesn't follow the datasheet requirements. Although the current one is working normally, there could be issue happening if you are going to do volume production.

Thanks & Regards,

Xiaoyan

[NM11]

Hi Xiaoyan-san,

I attached the power waveform.
Best Regards,

Naoki

[lixy]

Hi Naoki,

This waveform has obvious drop, which does not met the recommended "monotonic" standard.

We do not recommend device working under such power-up condition.

This may decrease the stability of configuration.

Thanks & Regards,

Xiaoyan

[NM11]

Hi Xiaoyan-san,

Thank you very much for your reply.
Let me confirm two points.

1. There are some parts like this that are not monotonic, but these seem to depend on other power supplies that are input to the FPGA.
Please see the attached file. Waveforms are added in the lower left corner.
The Intermediate voltage of "VCC_2V5" and "VCC_1V5_FPGA" is generated when "VCC_1V15" is turned on.
In the electrical circuit, these power supplies are only connected within the FPGA.
So we intend to set the power supply from our system to the FPGA as specified.

2. What are the specific events you are referring to below?

For example, does the FPGA not work at all?
(The output signal from the FPGA does not change when a signal is input.)

We have built a prototype using about 100 of these FPGAs, and there does not seem to be any failure.
Is this a very rare event that can be resolved by rebooting?

Best Regards,

Naoki

[NM11]

Hi Xiaoyan-san,

I am sorry.
Let me add a few things.

I am referring to the following in 2.

> This may decrease the stability of configuration.

Best Regards,

Naoki

[lixy]

Hi Naoki,

Sorry for late response. I was confirming the problem with more senior engineers. Here's our answer.

According to the waveform and description you provided, the "slight drop" is possibly the "IR Drop" caused by reference floating, which means it could be only a measurement error. Another possibility could be that the Voltage Regulator‘s output efficiency is not high enough. Therefore you may not need to worry about this "slight drop".

However, there could be another potential problem that the "VCC_0V75" does not seem to start from GND. Please also check this to make sure this power rail is not affected by other power supplies.

Regarding to the problem that how "non-monotonic power supply" will affect the FPGA, we still do not have an clear answer though.

Thanks & Regards,

Xiaoyan

[NM11]

Hi Xiaoyan-san,

Thank you for your answer.

I will check the "VCC_0V75".

Please continue to confirm the influence of "non-monotonic power supply".
Please also consider the following as described on April 5
> So we intend to set the power supply from our system to the FPGA as specified.

Best Regards,

Naoki

[NM11]

Hi Xiaoyan-san,

I checked the "VCC_0V75".

This power rail is not connected to other power supplies on schematic.
The cause of the floating from GND was that this power rail was taking a long time to discharge (about 1 minute).
When I turn on the system before the power rail finishes discharging, the voltage rises from about 0.2V.
Is there a problem with a maximum of about 0.2V?
The system appears to be working fine in that case.

So, this power rail is not affected by other power supplies.

I would also appreciate your response to the following questions I have asked you in the past.
> Please continue to confirm the influence of "non-monotonic power supply".
> Please also consider the following as described on April 5
>> So we intend to set the power supply from our system to the FPGA as specified.

Best Regards,

Naoki

[lixy]

Hi Naoki,

Sorry for late response.

I communicated further with our team.

About the "monotonic" issue, the power-up process will work fine as long as the power reaches the required voltage level within Ramp Time.

As I mentioned before, we checked the power waveform you provided and only 0.75 V power rail seems to be risky. The "0.2 V" might be a leakage from other power rails, which currently does not seem harmful to the device. However, there might be a risk that this leakage get higher since we do not know how the leakage is caused.

Thanks & Regards,

Xiaoyan

[lixy]

Hi there,

If there's currently no further requests, I am setting this issue to resolved.

By the way, we would appreciate it if you can take a moment to fill in the survey about this IPS case, which will be sent to your email. Your feedback is valuable and helps us improve our support quality. 

Best regards,

​​​​​​​Xiaoyan

[NM11]

Hi Xiaoyan-san,

Thank you very much for your kind response.
Please allow me to check a little more as it is complicated.

As per "Power waveform_20230405.jpg", "VCC_1V5_FPGA" ramp time is 200ms, so it exceeds the specified value of 100ms.

What is the effect by this exceeding?
Our prototype seems to be working fine so far.

I received the following answer previously, what exactly is "device configuration to fail"?
> As you can see from the Figure 11-7 in the Arria V handbook, POR delay and Configuration time will follow the tRAMP. If tRAMP is not met, the I/O pins and programming registers remain tri-stated, which may cause device configuration to fail.
For example, does the FPGA not respond to input signals at all?

Best Regards,

Naoki

[lixy]

Hi Naoki,

If configuration fails, the FPGA would not fulfill the logic in your design.

When tRAMP requirement of the FPGA device is violated, FPGA would not be able to start Configuration. Even if you find that the FPGA is successfully configured when you violate the requirement in Datasheet, we can not promise all the FPGA devices will work properly in this condition.

Thanks & Regards,

Xiaoyan

[NM11]

Hi Xiaoyan-san,

Thank you for your reply.
We changed the design and was able to reduce the ramp time to within 100ms.
Therefore, I think it is OK since we were able to meet the requirements in the Datasheet.

Thanks,

Naoki