Before I’m starting to describe my problem let me tell you, that I’m working with the Quartus II v8.1 Web Edition, the Altera DE2 Board (especially the ADV7181B Video Decoder) and the PAL-Output of a Panasonic Digital Camera.To prepare my work I tried to find out how many clock cycles appear in one video line (PAL). It’s a very simple design – a normal counter which resets with HSYNC and displays the value with the red LEDs. The simulation was already successful, but when I download my design into the FPGA the following problem occurs: some LEDs are flickering and some are active all the time. If I would ignore the flickering ones, my counter would show the correct length of a PAL-Line. My question is now, shouldn’t have every line the same length? Why are there some LEDs flickering? Is it a problem of the video decoder, my camera or is it a mistake in my design? My design file is in the appendix. I really hope someone can help me, because this problem cost me a lot of time until now. Thanks a lot. Alex
I think it's better to upload a simpler design, without counting the lines. Now I only count the clock cycles during a single line.The Datasheet of the Decoder says that there are 1728 clock cycles per line. When I ignore the blinking LEDs my counter puts out 1726. That would be right, because I don't count during the HSYNC interval. But as I already mentioned all the other LEDs are blinking, which means that there must be some lines with different lengths. And that doesn't make any sense to me. The ADV7181B Video Decoder runs nearly in default setup. Can it be the PAL Output of my camera, which lets the decoder do such things? Or have I a mistake in my design. Thank You
I think if the decoder is in default setting it is needed to work on falling edge clock and not rising_edge. At least at the ADV7180 so probebly this one is the same. please update if it helps?
Thank you very much. But there is no problem with my code. Today I found the real failure.I have looked at the CLOCK signal and the HSYNC signal with an oscilloscope and found out, that the clock is total asynchronous to the HSYNC. When I triggered to one of them, the other one runs totally away. But I tried it with several DE2 Boards in the laboratory and realized another fact. Altera made two revisions of the DE2 Board. My Board was revision 1. But today I tried it with some boards of revision two and tada: the HSYNC comes with the falling edge of the clock. No running away of the other signals. So I think it would be better for me to use the DE2 Board Revision 2 for working with the Video Decoder :) I'm so glad, that I found this mistake. I would never thought of that. I'm out. Alex PS: i attached the fotos, for the proof of all that :) the first one is with Revision 2 and the second picture is with Revision 1.
hello , i hope you are doing well, i'm mustapha from algeria and i gave a project to do , it's about image and video processing , i take a picture by a camera in real time and i use the board de2 to display it on the screen , after that i do some functions like using filters , convolution and others , i must use the decoder adv7181b of de2 , i need help for that because i'm a begineer, if you have time can you help me , thank you.