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5234 Discussions

Transceiver speed on Stratix 10 h-tile dev kit

SDe_J
Novice
527 Views

Hello Intel Forums,

 

I have a stratix 10 h-tile dev kit (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1...).

 

 

I would like to use a transceiver to send/recieve data at 10.24GHz. I've written the transceiver PHY to take 32 bit frames at 320MHz, then serialize it at 10.24GHz. This was developed and tested in a simulation, and worked fine.

 

When I got the stratix 10 board, I decided to use the QSFP for the physical connection. The QSFP has a reference clock which runs at 644.53125MHz. My question is, do I have to use this clock to run the transceiver, or can I use a clock from the FPGA? If I have to use this reference clock, can I use a PLL to run it at a different frequency?

 

Thanks for your assistance,

-Sam

 

 

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3 Replies
CheePin_C_Intel
Employee
116 Views
Dear Sam, As I understand it, you have some inquiries related to the QSFP refclk for the S10 H-tile devkit which is running at 644.53125MHz by default. You would like run the refclk at 320MHz. Please correct me if I am wrong, I believe you are referring to the REFCLK_QSFPI1 (644.53125 MHz LVDS) which is the OUT1 of Si5341A. If yes, for your information, you may try to use the Clock Controller to change it to other frequency that you are targeting. You may refer to "Clock Controller" section and "Figure 32. Clock Controller - Si5341" in the Intel® Stratix® 10 GX FPGA Development Kit User Guide for further details. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
SDe_J
Novice
116 Views

Hi Chee,

 

Thank you for your reply, it was very helpful. I assume this is a volatile setting - if I cycle the board power the clock will reset to 644.53125MHz. Is this correct?

 

-Sam

 

 

CheePin_C_Intel
Employee
116 Views
Hi, Yes, your understanding is correct. It is volatile and reset to default after power cycling the board.
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