Hello Intel Forums,
I have a stratix 10 h-tile dev kit (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1...).
I would like to use a transceiver to send/recieve data at 10.24GHz. I've written the transceiver PHY to take 32 bit frames at 320MHz, then serialize it at 10.24GHz. This was developed and tested in a simulation, and worked fine.
When I got the stratix 10 board, I decided to use the QSFP for the physical connection. The QSFP has a reference clock which runs at 644.53125MHz. My question is, do I have to use this clock to run the transceiver, or can I use a clock from the FPGA? If I have to use this reference clock, can I use a PLL to run it at a different frequency?
Thanks for your assistance,
Thank you for your reply, it was very helpful. I assume this is a volatile setting - if I cycle the board power the clock will reset to 644.53125MHz. Is this correct?