Programming FPGA Flash in arria 10 soc development kit

[Altera_Forum]

Hi, 

 I am new to this arria 10 soc development kit, I want to program arria 10 programming flash.  Which is the programming flash for arria 10 FPGA and how to program it.  Thanks, Kamal

[Altera_Forum]

Hi, 

 Flash is EPCQ device and to programming steps refer https://www.altera.com/content/dam/altera-www/global/en_us/support/boards-kits/arria10/soc/es2_files... https://rocketboards.org/foswiki/documentation/a10gsrdbootlinuxfromsdcard170  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Hi ,  

I'm also new to the Arria 10, i need some help on how to program the FPGA side of the board, i you have found Good tutorials please share it.  Thank you,

[Altera_Forum]

Hi Anand, 

 Thanks for the reply .  I am referring an370.pdf "Using the Intel FPGA Serial flash loader with Intel quartus prime software"  https://alteraforum.com/forum/attachment.php?attachmentid=14945&stc=1   I am having aria 10 soc development kit, where EPCQ flash cant be programmed directly through JTAG.  have also referred this video by intel fpga, active serial configuration using jtag: "https://www.youtube.com/watch?v=dpsfcgnqocu" have followed the steps.  But in this video it never mentioned to instantiate altera or intel FPGA Serial flash loader (thought that programmer automatically takes care of it when jic file is used).  But in an370.pdf it is mentioned to instatntiate  https://alteraforum.com/forum/attachment.php?attachmentid=14946&stc=1    Do we need to instantiate the core, share the asmi interface, and map the pins manually or it is taken care automatically.  As per the tutorial video.  Step 1: Compile the Design  Step 2: Convert to jic file  Step3: Programmer, autodetect, change file and give jic file.  https://alteraforum.com/forum/attachment.php?attachmentid=14947&stc=1   programming was stopped at 94%  Error message: https://alteraforum.com/forum/attachment.php?attachmentid=14948&stc=1   Please give inputs, and refrences where the process is mentioned clearly, also point out where we are going wrong.  Thanks, Kamal Chandra

[Altera_Forum]

Hi Kamal, 

Thank you for the reply , after compiling the hardware design there is a new .sof file and no jic. what's a jic file ? and when programming the FPGA is there any initialization for HPS ?