Quartus 18.1 7-segment display

[Chanakya1]

Hello, 

I am using De1 SoC FPGA board - 5CSEMA5F31C6. On Quartus 18.1, I have designed a schematic for integral and getting a expected simulation output. But when I try to program it on FPGA, I am not getting correct output. I am using 7 segment HEX display to capture 32-bit of output. 

Can someone help me to solve this 


THank You

[sstrell]

Show your code.  And use Signal Tap to make sure signal levels are what you expect.

[HubertG]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

[HubertG]

Hi Chanakya1,

Can you provide us your design coding in order for us to provide better support and debugging for you ?

Thank you in advance

Hubert

[HubertG]

Hi Chanakya1,

Can you help on the request above in order for us to give you a better support on debugging ? ^-^

Thank you in advance

Hubert

[HubertG]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.