Quartus simulation differs from board results

[Armando1989]

Hi there!

Recently purchased board from Aliexpress with EPM570T100C5 in it

Just programmed simple overflow accumulator as used in old fractional N synthesizer schemes. Mine with registered ouput for overflow so is one clock delayed.

module frac_acc(clk, reset, clk9600, prog, overflow, add);

input clk; //50MHz on board

input reset; //external reset pin

input [3:0] prog; //programing 4 bit add value

output reg [3:0] add;  //adder result which feedbacks and adds to prog value each clk9600 cycle

output reg overflow;  //overflow output

output clk9600;  //9600 clock divide from 50MHz

reg [12:0] c=13'b1111111111111;

always @(posedge clk) begin 

if (c>=5207)

c<=0;

else

c<=c+1;

end

assign clk9600 = (c <= (5208/2)-1)? 1'b1:

1'b0;

always @(posedge clk9600) begin

if(reset==1)

add<=0;

else

{overflow, add}=add+prog; 

end

endmodule

Testbench:

`timescale 1ns/1ps
`define clk_period 20

module testbench;

reg clk;
reg reset;
reg [3:0] prog;
wire [3:0] add;
wire clk9600;
wire overflow;

frac_acc uut(.clk(clk), .reset(reset), .clk9600(clk9600), .prog(prog), .overflow(overflow), .add(add));

initial clk = 1'b1;
always #(`clk_period/2) clk = ~clk;

initial begin
reset=1;
#105000
reset=0;
#20;
prog = 4'b0000;
#10;
prog = 4'b0001;
#380000
reset=1;
#440000
reset=0;
end

endmodule

When simulated with tesbench result is as expected, for each 16 clk9600 cycles,  overflow is set "PROG" value times. Ie: if PROG is prog = 4'b0001; then 1 time overflow is set each 16 clocks, as below image

 Problem arrives when i program into board... Instead of each 16 cicles; above is true just for half cicles, as if adder was 3 bits not 4.

So if i want actual chip to behave as per image, i need to set add[4:0] and prog[4..0] and reprogramm it, and so on

Anyone has experiences such behavior?

besides above, seems if input pins are not tied to ground it doesnt read as 0, so need tie to gnd for propper operation, no sure if pull down resistor or pin type is in order here.

Thanks!

 

[FvM]

clk9600 has most likely glitches in real hardware. Try to set in registered rather than combinational assignment.

[Armando1989]

Hi FvM

Yep, that did the trick

  always @(posedge clk) begin
  if (c>=5207)
  c<=0;
  else
  c<=c+1;
  clk9600 <= (c <= (5208/2)-1)? 1'b1:
  1'b0;
  end

The change added output through flip flop as per rtl netlist. so whatever glitch happened at logic it was stable after delayed clock. Its not first time i experience glitches, on this same design the carry propagation delay does a glitch, bigger chance when more adders in series, but after passing trough one clk delay it gives the room stabilize logic level so it is valid.

Im quite new on quartus and didnt see the glitches on real scope at first, and since simulation appeared fine i was a little puzzled.

I wish i know how to account for glitches at simulation level... 

Thanks!