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Hello,
I have selected the FPGA part number 10M08DAF256I7G for our design. I would like to confirm whether a specific power-up sequence is mandatory for this device.
If a power-up sequence is required, could you please share the recommended sequence to be followed? I came across a reference in one of the documents suggesting a specific order, as shown in the image attached below. Kindly confirm if this is the correct and necessary procedure.
or is this the sequence to be followed?
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Hello,
For the 10M08DAF256I7G (MAX 10 production device), a specific power-up sequence is not required, unlike early engineering sample (ES) devices, all power rails (VCC, VCCINT, VCCA, VCCIO, etc.) can be ramped up in any order or simultaneously, provided that absolute maximum and recommended operating conditions are not violated. The sequencing shown in the attached images applies only to ES devices; for production devices, you may power the rails without a defined sequence. Please ensure that all supplies are stable before configuration begins.
Reference: https://www.intel.com/content/www/us/en/docs/programmable/683400/18-0/hot-socketing.html
Regards,
Aqid
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Hello,
I wish to follow up with you. Do you have any updates?
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I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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