Questions for JTAG signals timing constraints.

[RLee42]

Hi,

I'd like to have several Cyclone V FPGA normal PINs, not the ones for altera jtag, as the JTAG signals, and I hope the TCK can work at a 5MHz~10MHz frequency. My questions are as below:

1. Is there any official recommendation for the timing constraints or settings for the normal PINs when they are used as TCK, TMS, TDI, TDO?------Like max/min input/output delay if needed, and source synchronous may be needed, also TDI and TDO are something like DDIO. How can I handle these things all together?
2. If I don't assign a dedicated clock PIN for TCK and no special treatments for the JTAG signals, what's the possible maximum frequency of TCK from the side of FPGA?

Thank you.

Best regards,

Ross​

[Kenny_Tan]

You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf?wapkw=set_input_delay+altera_reserved_tdi page 17