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Remote System Update


I am trying to create a remote update controller for a Cyclone 10 LP.  I have done this successfully for both Cyclone V and Max-10 devices.  My system consists of a NIOS and accompanying memory, PLL, etc. as well as an EPCQ Controller and the Remote Update IP. 

When I try to stimulate a reconfig via a NIOS register write, nothing happens.  I have tried various things but ultimately have come across the following from the Knowledge base (Bug ID: FB: 2007757536):



No, Intel® Cyclone® 10 LP FPGA devices do not support HAL drivers for Remote System Update.


To perform Remote System Update in Intel Cyclone 10 LP FPGA devices use the Avalon MM (AVMM) interface and connect to user logic or an AVMM master. The Cyclone 10 LP Remote System Update example design can be downloaded from the Intel FPGA Design Store.


I checked the design store for the example design and found that the IP was instantiated in the FPGA and controlled by simple logic.

Based on the problem description above (Cyclone® 10 LP FPGA devices do not support HAL drivers for Remote System Update), can I assume that I cannot stimulate reconfiguration via a NIOS register write?

If not, can I get more information about the solution presented in the example design such as timing diagrams and a register read example?

Thanks in advance.

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