Request of AXI bridge example for CycloneVsoc HPS to FPGA communication

[CAlex]

Hi

I've tried the AVALON MM bridge HPS to FPGA translating 32 bit data for each using alt_write_word() and alt_read_word().

There is ~2us latency between orders(128bit wide H2F bridge with 50MHZ clk, with 925MHZ HPS),which is tested by signal tap.

And it seems dont allow the burst transfer and stream transfer because INTEL HWLIB dont support this.

It is bad for my design, for I need read and write 10 words of data from the FPGA, and calculate every 50 us.

I heard AXI bridge is available and it is faster than the Avalon, but I didnt find any guide for CycloneVsoc.

Do you have any resource or offer the help for that?

Reguard

ALEX

[JingyangTeh]

Hi Alex

I am Jingyang and I am assigned to work on this case.

Please give me sometime to get back to you on the question above.

Regards

Jingyang, Teh

[JingyangTeh]

Hi Alex

I would suggest you to try use the alt_read_dword to see if it is improving on your end.

For the bridges for the HPS to FPGA communication the bridges are already AXI.

However because the api of the alt_read uses word wise read and write over the bridges. It does not fully utilize the AXI feature of the burst and stream.

Regards

Jingyang, Teh

[CAlex]

Hi，

I'm not sure how to correctly use the burst and stream function of the H2F bridge. 

Now what I do is making a FPGA memory 

|                                                                |         32 bit read            |                                                            |   128 bit wide       |                        |
| FPGA MEM [depth:0][width:0]    S  |  ==============>  |M   AVA MM PIPELINE BRIDGE   S|  ==========>    |M   HPS H2F |
|                                                                |         32 bit write           |                                                            |                                 |                        |

If Im going to use burst transmit, other than changing the 32 bit R/W tunnel to 64 bit( if I'm going to use alt_write_dword ), what else should I do in FPGA & HPS Baremetal  SOC? 

Do you have any examples on that? 

Thank you 

Reguards

Alex

[JingyangTeh]

Hi Alex

I see that the flow of data is from the FPGA to the HPS.

There is this example of moving data through the FPGA to HPS bridge instead of the HPS to FPGA bridge.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html

It uses the SGDMA example. You might want to take a look at the cacheable route.

It uses the SGDMA IP to pass data from the FPGA fabric to the HPS memory location.

Then from the HPS you could access the data directly from the memory location.

Regards

Jingyang, Teh

[CAlex]

Hi

Thnak you for your example, I'll check it soon.

The other question might be :

If Im going to burst transfer a 64bit buffer,  what should I do on HPS side?

Is that just alt_write_dword() with at least 64 bit wide H2F AXI Master?

If so then what is the difference of burst transfer like that and normal transfer?

Thank you .

Reguards

Alex

[JingyangTeh · Accepted solution]

Hi Alex

The dword read is the maximum size that is available by the library to read through the bridge.

Is reading using the dword improve the situation on your end?

The difference between a normal and burst command is the in the burst command there are addtional signals such as ARBURST, ARSIZE ,RLAST.

In the burst command it will have state the number of burst read from the receiver to send the data.

https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI-Burst-Transfers

Regards

Jingyang, Teh

[CAlex]

Hi, Jingyang, Teh

If I set H2F AXI bridge to 64 bit, then it will double the speed, although it still dont meat the request. 

Now Im trying to increase the clk frequency of the Platform Designer.

And I'll check your example as well.

Thank you for yr help

Reguard

Alex

[JingyangTeh]

Hi Alex

Please do take a look at the example.

There would be some delay in between each read.

By using the DMA it will speed up the process and also free up your resource for other stuff.

Regards

Jingyang, Teh

[JingyangTeh]

Hi Alex

Any update on this case?

Do you have any question on the example design?

Regards

Jingyang, Teh

[CAlex]

Yes , a lot of questions, mainly about what do these IP do and how to do it properly.

I need more time for this example,

but the understanding itself is not related to this thread.

I'll open a new thread if there are quesions I can't figure out.

Please do what you need to do to this thread.

Thank you for your help.

Reguards.

[JingyangTeh]

Hi

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang, Teh