Running a Quartus design flow from .TCL

[Vadi96]

Hi,

I have the built quartus project and the entire design flow I want to run it through .TCL flow.

I have exported the project to .TCL from the quartus > project >generate TCL for the project.

.TCL :
# Quartus Prime: Generate Tcl File for Project
# File: dummy.tcl
# Generated on: Tue Sep 24 16:05:30 2024

# Load Quartus Prime Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "dummy"]} {
puts "Project dummy is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists dummy]} {
project_open -revision dummy dummy
} else {
project_new -revision dummy dummy
}
set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
set_global_assignment -name TOP_LEVEL_ENTITY dummy
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:12:07 SEPTEMBER 24, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "23.4.0 Pro Edition"
set_global_assignment -name VERILOG_FILE dummy.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE 10AX115H1F34I1SG
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
# IOBANK_3E
set_location_assignment PIN_F8 -to b -comment IOBANK_3E
# IOBANK_2I
set_location_assignment PIN_AF21 -to a -comment IOBANK_2I
set_instance_assignment -name IO_STANDARD "1.8 V" -to b -entity dummy
set_instance_assignment -name IO_STANDARD "1.8 V" -to a -entity dummy

# Including default assignments
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON -family "Arria 10"
set_global_assignment -name TDC_CCPP_TRADEOFF_TOLERANCE 0 -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL ON -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ON -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_SYNTHESIS_REGISTER_PACKING OFF -family "Arria 10"
set_global_assignment -name PHYSICAL_SYNTHESIS OFF -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" -family "Arria 10"
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL OFF -family "Arria 10"
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING AUTOMATIC -family "Arria 10"
set_global_assignment -name ENABLE_PHYSICAL_DSP_MERGING OFF -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS ON -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ -family "Arria 10"
set_global_assignment -name GENERATE_PR_RBF_FILE OFF -family "Arria 10"
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -family "Arria 10"
set_global_assignment -name POWER_AUTO_COMPUTE_TJ ON -family "Arria 10"

# Commit assignments
export_assignments

# Close project
if {$need_to_close_project} {
project_close
}
}

1. how to run this .TCL to go through design flow till assembler?

2. In Xilinx Vivado, command lines are printed in TCL console as soon as something is executed in GUI. Then later on we can copy the entire .tcl command lines from the console and then put it under one .TCL file and then later can source this file in Vivado TCL console.
Is there a similar way in Quartus too?
(Intention : Instead of going through and understanding all the command lines in the quartus scripting document, some easy way?)

[Vadi96]

Hi Team,

Any update on this? Waiting for answers

[RichardTanSY_Altera]

1. Use the quartus_sh executable with the --flow option to perform a complete compilation flow with a single command.

The following example runs compilation, timing analysis, and programming file generation with a single command: 

quartus_sh --flow compile filtref

where <filtred> is the Quartus Prime project name.

2. Unfortunately, there is no tcl command showed in Quartus GUI. The command-line and TCL API manual can be opened by "quartus_sh --qhelp".

Command line and Tcl script user guide is in https://www.intel.com/content/www/us/en/docs/programmable/683432/current/command-line-scripting.html

You may checkout the Scripting section for further information:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/quartus-support.html

There are guidance and some examples for your reference. 

Regards,

Richard Tan

[RichardTanSY_Altera]

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side?

Regards,

Richard Tan

[RichardTanSY_Altera]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan