SDRAM to OCM via DMA

[K606]

I am in the process of learning about communication between SDRAM and OCM via DMA, using the Agilex-5.

The idea will be to write 0xdeadbeef to the SDRAM, then initiate a DMA transaction between the SDRAM and OCM, and then confirm that the OCM has received the data. 

This is what have implemented so far in Quartus:

This design compiles without errors. 

My current understanding of the agilex_hps_f2sdram is that this is directly mapped with the base address displayed in Quartus. I.e. to 0x0.

I think this is roughly equivalent to the Test 2 in this design post, having the following arch:

Which states that the CSR register must be set 0x3C108208 to achieve direct access for writing to SDRAM. However, since I did not include the ICCT module in my design, I ignored this for now.

With all this in mind, I was hoping the following u-boot commands would do the trick:

## address map
#read_sdram         =0x00000000
#write_ocm          =0x21000000
#msgdma_csr         =0x22000000
#msgdma_descriptor  =0x22100000
#msgdma_response    =0x22200000

## msgdma offsets
#msgdma_csr_control=0x4
#msgdma_descriptor_read_high=0x14
#msgdma_descriptor_write_low=0x4
#msgdma_descriptor_write_high=0x18
#msgdma_descriptor_length=0x8
#msgdma_descriptor_control=0xc

# Read SysID (should read 0xACD5CAFE)
md 0x20010000 1
# Write to Read SDRAM
mw 0x00000000 0xdeadbeef 0x10
# Check 1st set of data
md 0x00000000 4

# Stop dispatcher
mw 0x22000004 0x1
# Stop descriptors
mw 0x22000004 0x20
# Reset Dispatcher
mw 0x22000004 0x2

# Write dma_read_pointer_low
mw 0x22100000 0x00000000
# Write dma_read_pointer_high
mw 0x22100014 0x0
# Write dma_write_pointer_low
mw 0x22100004 0x21000000
# Write dma_write_pointer_low
mw 0x22100018 0x0
# Write length in bytes 8
mw 0x22100008 0x8
# Check status
md 0x22000000 1

# Control, wait for resp
mw 0x2210000c 0x02000000
sleep 1
# Control, wait for resp and go
mw 0x2210000c 0x82000000

# Check status
md 0x22000000 1
# Read back from OCM (should read 0xdeadbeef)
md 0x21000000 1

However, the data in the final register seems to be returning garbage after running through the script:

...
SOCFPGA_AGILEX5 # md 0x22000000 1
22000000: 00000002 
SOCFPGA_AGILEX5 # md 0x21000000 1
21000000: 565ebaeb                             ..^V

I had considered that maybe it is an issue with access, however I have reserved the 1st GB of memory using the mem=1G uboot command. I was wondering if anybody had any idea where I have made a misunderstanding?

Many thanks!
K

[K606 · Accepted solution]

Tried this with a connection to the altera ace5 cct and it worked well.

I suppose it is an issue with cache after-all!