SPI-3-wire SPI_CS pin Configuration

[giomate]

Hi there,

Im need to configurate a SPI interface on a Cyclone V. On the deplyment, i did  some measurements and i noted that the SPI_SS_N is not toggling, no matter which flags i use.

int_result=alt_avalon_spi_command(base_address,slave,size,buffer,0,0,ALT_AVALON_SPI_COMMAND_MERGE);

int_result=alt_avalon_spi_command(base_address,slave,size,buffer,size,rx_buffer,0);

also, i configurate also the SPI_CS_n pin on the vhdl code, but  it is not working though ...

spi_adf5610_external_MISO => adf5610_spi_sdo,

spi_adf5610_external_MOSI => adf5610_spi_sdi,

spi_adf5610_external_SCLK => adf5610_spi_sclk,

spi_adf5610_external_SS_n => adf5610_spi_csn,

im tested succesfully a similar code on an Arduino. But, in these case the SPI_CS is driven as a GPIO, and the SPI port is enabled/disabled by request.

I wondering if i had to do something similar on the eclipse-nios2 code..

i appreciate any comment or sugestion

[BoonBengT_Intel]

Hi @giomate,

Thank you for posting in Intel community forum and hope this message find you well.
If i understand the situation correctly, I would recommenad that the following design example might be helpful to your needs.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html

Please do refer to the 'SPI_Bridge_Design_Example.zip', within the nios2 project there is a references C code to write and read to onchip memory connected via SPI for further details.

Warm regards.
BB

[BoonBengT_Intel]

Hi @giomate,

Good day, just checking in by any chances did you managed to look into the recommendation above.

Please do let us know if you have any difficulties doing so.

Thank you.

Warm regards

BB

[giomate]

hi BoonBeng,

thanks for your support,

at the moment , i got the spi working , when i modified the general SPI transfer function on that way:

void SPI_Handler::Open(void){

       IOWR_ALTERA_AVALON_SPI_CONTROL(base_address, ALTERA_AVALON_SPI_CONTROL_SSO_MSK);

}

void SPI_Handler::Close(void){

      IOWR_ALTERA_AVALON_SPI_CONTROL(base_address, 0);

}

void SPI_Handler::SEN(bool sen){

      if(sen){

            IOWR_ALTERA_AVALON_SPI_CONTROL(base_address, 0);

      }else{

            IOWR_ALTERA_AVALON_SPI_CONTROL(base_address, ALTERA_AVALON_SPI_CONTROL_SSO_MSK);

      }

}

however,  on higher baudrates(SPI_ADF5610_TARGETCLOCK >4000000u), something is not working...

So , if the system is 80 MHz, how fast can run the SPI?

[BoonBengT_Intel]

Hi @giomate,

Per my understanding, the SPi core is design to transfer single data word at a time.
As for the baud rates selection between clock, perhaps you can look at the relationship here.
Hope that helps.

Warm regards
BB

[BoonBengT_Intel]

Hi @giomate,

Greeting and hope this message find you well, by any chances did you managed to look in documents.

Please do let us know if there is any clarification we can help with.

Warm regards

BB

[BoonBengT_Intel]

Hi @giomate,

Hope this message find you well and good day, as we do not receive any response from you to the previous clarification that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 
 
Warm Regards
BB