ScanManager : read IDCode

[WabG]

Dear support,

On a SoC (Cyclone V) we want to access the JTAG chain from HPS through the ScanManager.

The procedure below is extracted from the documentation and is executed on U-Boot but no data is present in the "Read FIFO". Any help appreciated :

mw 0xFFF02004 0x80       # Enable scan chain 7 : SCANMGR_OFFSET_EN = 1
mw 0xFFD040A0 0xFF7    # Disable TCK clock
mw 0xFFD08030 1             # Connect FPGA JTAG pins
mw 0xFFD040A0 0xFFF    # Enable TCK clock

mw 0xFFF02000 0x2         # Reset TAP
mw 0xFFF02000 0x0         # Release reset TAP

# GOSTATE IDLE : write FIFO4BYTE 0x40404040 (TMS = 1111 1111)
mw 0xFFF0201C 0x40404040
mw 0xFFF0201C 0x40404040

# GOSTATE SHIFT_DR : write FIFO4BYTE 0x00400000 (TMS = 0100)
mw 0xFFF0201C 0x00400000

# Output IDCODE : write 8x FIFO4BYTE 0x90909090 : 32 x (TMS = 0, TDI = 1)
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090

# Read FIFOCNT : bits[26:24] = 0 => FAIL !
md 0xFFF02000 1

Regards,

WabG

[Farabi]

Hello,

May I know what device are you using? Do you know the part number?

regards,

Farabi

[WabG]

Farabi,

Yes, this is a Cyclone V 5CSEBA5U23I7.

Regards,

WabG

[NurAiman_M_Intel]

Hi,

Ypu said the above procedure was extracted from documentation, may I know which document? Please provide the link.

Do you also refer to below document?

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/hard-processor-system-technical-reference.html

Regards,

Aiman

[WabG]

Hello,

Yes this the only document I have found about the Scan Manager. In detail, i'm refering to chapter "Communicating with the JTAG TAP Controller" for the procedure but I have read the whole document.

Regards,

WabG

[WabG]

Aiman, Farabi,

Can you provide me with an example to use the module ScanManager ?

You should have this information as it is mandatory for the development and verification teams to test each feature implemented in the silicium of the devices.

Otherwise, is there any other support team I can contact ?

Regards,

WabG

PS : this isn't the first question I see in this forum without any answer. Having a good support is a big concern for the choice of Intel for the future development.

[Farabi]

Hello,

I am sorry to keep you waiting.

I can replicate your issue at Cyclone V SoC devkit.

We already filed internal bug report for this IP. Report case#: 15016436045

We are waiting for engineering to look into this and give the solution.

regards,

Farabi

[WabG]

Farabi,

When will you give a status on this issue ?

Regards,

WabG

[WabG]

Farabi,

Any update ?

WabG

PS : without any answer, the support strategy is clearly to let die all "not obvious" topics. As reminder, the issue has been opened 2 months ago.

[Farabi]

Hello WabG, 

Apologize you need to wait for long time. Please refer attached scan_manager.v design. 

regards,

Farabi

[Farabi]

Hello,

I am pushing engineering to support this issue. I will update once we get update from engineering.

regards,

Farabi

[Farabi]

Hello,

I am returning this case back to community for continuous support. If you still have question, please raise new ticket, we will be happy to help.

regards,

Farabi