FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

ScanManager : read IDCode

WabG
Beginner
189 Views

Dear support,

 

On a SoC (Cyclone V) we want to access the JTAG chain from HPS through the ScanManager.

 

The procedure below is extracted from the documentation and is executed on U-Boot but no data is present in the "Read FIFO". Any help appreciated :

 

mw 0xFFF02004 0x80       # Enable scan chain 7 : SCANMGR_OFFSET_EN = 1
mw 0xFFD040A0 0xFF7    # Disable TCK clock
mw 0xFFD08030 1             # Connect FPGA JTAG pins
mw 0xFFD040A0 0xFFF    # Enable TCK clock

mw 0xFFF02000 0x2         # Reset TAP
mw 0xFFF02000 0x0         # Release reset TAP

 

# GOSTATE IDLE : write FIFO4BYTE 0x40404040 (TMS = 1111 1111)
mw 0xFFF0201C 0x40404040
mw 0xFFF0201C 0x40404040

 

# GOSTATE SHIFT_DR : write FIFO4BYTE 0x00400000 (TMS = 0100)
mw 0xFFF0201C 0x00400000

 

# Output IDCODE : write 8x FIFO4BYTE 0x90909090 : 32 x (TMS = 0, TDI = 1)
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090
mw 0xFFF0201C 0x90909090

 

# Read FIFOCNT : bits[26:24] = 0 => FAIL !
md 0xFFF02000 1

 

Regards,

 

WabG

 

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Farabi
Employee
139 Views

Hello,


May I know what device are you using? Do you know the part number?


regards,

Farabi


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WabG
Beginner
111 Views

Farabi,

 

Yes, this is a Cyclone V 5CSEBA5U23I7.

 

Regards,

 

WabG

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NurAiman_M_Intel
Employee
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Hi,


Ypu said the above procedure was extracted from documentation, may I know which document? Please provide the link.


Do you also refer to below document?

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/hard-processor-system-technical-reference.html


Regards,

Aiman


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