Stratix 10 DDR4 timing model & package model

[asorouri]

Hi

I am running board level DDR4 simulation with a Stratix 10 SoC and a Mercury 4N1G72T-24B3I SDRAM device. I need timing model and package model for this SoC. I prefer a s-parameter package model if its passivity and causality checked and proven.

[AdzimZM_Intel]

Hi

We are providing the IBIS model for Stratix 10 device and other FPGAs in our website.

You can search and download the IBIS model in the link below to run the board simulation.

Link: https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html

UG: https://www.intel.com/content/www/us/en/docs/programmable/683768/23-1/simulation-with-ibis-models.html

I believe you are requesting for DDR4 timing model as well, but this is not something that we can provide since the DDR4 model is based on the vendor and you should request the model from the vendor.

Regards,

Adzim

[asorouri]

Hi Adzim,

Thanks for the link to the models.

After thinking about it more, I came up with this idea that since this is an FPGA device, one simulation model received from you could not be applied to all applications and FPGA programming. We (our FPGA developer team) should be generating it by the tool they used to develop this FPGA, so the model pins match the programmed FPGA pins. Do you agree and does the tool have this option?

There is also ODT issue in my simulation. The option to select/change ODT in the simulation tool is grayed out. This reinforces my idea of having to generate the IBIS model in the tool used to develop the FPGA after it is fully developed.

As for DDR4 timing model, there is a SDRAM DDR4 timing model and Controller DDR4 timing model. In this case the FPGA is the controller. However, some vendors direct the user to follow the JEDEC standard some provide their own version. If Altera/Intel does not supply such model, then I will use the JEDEC standard which is the default model in the simulation tool.

Thanks

Ali

[AdzimZM_Intel]

Hi Ali,

I believe the tool that you mentioned is Quartus software.

The Quartus has the IBIS Writer that can be used to generate the IBIS model.

It's can generate the model based on the design that you have in Quartus.

You can refer to this link to generate a custom IBIS model.

Link: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#eda/boardlevel/ibis/eda_pro_ibis_out.htm?erpm_id=10673258_ts1747729761093#eda/boardlevel/ibis/eda_pro_ibis_out.htm

This IBIS model is representing the FPGA side. For memory side, usually we use the vendor provided IBIS model. You may use JEDEC standard model in this simulation.

Regards,

Adzim

[AdzimZM_Intel]

Hi Ali,

Is there any further question in this thread?

Regards,

Adzim

[asorouri]

No, I am good.

thanks

[AdzimZM_Intel]

Hi Ali,

I will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,

Adzim