convert avalon bus to AXI4-Lite

[ZhiqiangLiang]

Hi,

My FPGA model is:

Cyclone 10 LP 10CL120.

I am now using Quartus II 18.1.

In FPGA, I added NIOS II, and  I would like to convert avalon bus to AXI4 LIte master. It means that NIOS will send out avalon signal, and the receiver is AXI4 Lite master.

the questions are:

1) is there any in chip IP adapter that can convert avalon to axi4 lite master?

2) if there is no IP adapter in chip, is there any sample code or reference?

[sstrell]

An AXI4-Lite manager (they don't call it master any more) would not be able to receive commands.  That would be an AXI4-Lite subordinate that receives and processes commands.  You can connect the Avalon host (previously referred to as master) interfaces to AX4-Lite subordinate interfaces directly in Platform Designer.  No adaptor is needed since the interconnect will get built automatically to support this.

And if possible, if this is a new design, you should use a newer version of Quartus and use a Nios V processor instead.

[ZhiqiangLiang]

Thank you @sstrell 

Is there any tutorial or example about how to operate Platform Designer to connect AXI4 Lite subordinate?

It took me a few day in the past to try how to user Platform Designer.   but I still don't know how to use it.

[sstrell]

You simply make standard connections in the tool between the interfaces of the components that need to be connected.  The user guide is here: https://www.intel.com/content/www/us/en/docs/programmable/683364.html

There's training here: https://learning.intel.com/Developer/learn/courses/389/creating-a-system-design-with-platform-designer-getting-started

[ZhiqiangLiang]

Thank you @sstrell 

I am now creating a new NIOS II project.

If I add EPCS to the project, I experience the issue "EPCS is not supproted in Cyclone 10 LP family".

The question is:

if I don't add EPCS, what should be added to burn firmware?

[sstrell]

Your configuration options are here: https://www.intel.com/content/www/us/en/docs/programmable/683879/current/configuration.html

[RichardTanSY_Intel]

Thank you Sstrell for the answers.

@ZhiqiangLiang, do you have further inquiry?

Regards,

Richard Tan

[ZhiqiangLiang]

@RichardTanSY_Intel 

Thank you!

I have many questions to use Cyclone 10 LP 10CL120.

My company buy the FPGA, and produce the PCB board. however, we can't power on it.

For example, my questions are:

1) whether we should connect a crystal oscilator to which pin of FPGA.

2) how to use Quartus to constrain signal node to GPIO pins.

3) I would like to run NIOS II in FPGA, however I don't know how to enable burning firmware interface.

4) and etc.

Our product previously used ZYNQ7000 of Xilinx, but Now, we are going to use Cyclone10LP.

Would you please contact me by my email: dpstill@126.com.

By the way, I previously worked in Intel as well.

[RichardTanSY_Intel]

1) You can assign it to the Dedicated Clock pin. You can check this in the Pin Planner > Task window> Highlight Pins > Clock Pins

2) Same with (1) You can assign pins using Pin Planner. Go to Assignments > Pin Planner.

Find your signal (e.g. led[0]) and assign it to a physical pin (e.g. PIN_AJ5).

Alternatively, you can manually constraints via .qsf constraints file:

 set_location_assignment PIN_AJ5 -to led[0]

https://www.intel.com/content/www/us/en/docs/programmable/683492/18-1/assigning-i-o-pins.html

Additionally, you can refer to the user guide below to check the legality of pin assignments, using I/O Assignment Analysis:

https://www.intel.com/content/www/us/en/docs/programmable/683230/18-1/guideline-use-i-o-assignment-analysis.html

3) As this question is related to configuration area, unfortunately, I am not expert in that particular area . Could you help to create a new forum case so an agent will be assigned to your case. Thank you for your understanding. 

Regards,

Richard Tan

[ZhiqiangLiang]

Thank you @RichardTanSY_Intel 

I have tried Pin Planner. The problems about Pin Planner are:

1) I don't know how to assign clk to which FPGA pin.

2) For example, the input crystal oscillator is  26MHz, but FPGA internal needs 160MHz. how to set FPGA PLL?

3) in Pin Planner, I can set some general GPIO, but the exported file is TCL which is not sdc file. should I convert the TCL file to sdc file? what is the difference? 

4) If I would like to manually write sdc file, what is format of sdc file? how to write the beginning of the sdc file?

5) once I finish the sdc file or Pin Planner, how to use it in Quartus?

[sstrell]

1) You can drag and drop signals to make pin assignments in the Pin Planner.  Dedicated clock input pins are indicated with a little waveform symbol on them.

2) The PLL is an IP you can parameterize so you can set what the output frequency should be based on the input frequency.

3) There's no need to export any files from the Pin Planner.  The assignments are placed in the .qsf file as Richard mentioned.  And a .sdc file is for timing constraints.  It has nothing to do with pin assignments other than using the names of the top-level I/O signals for creating I/O timing constraints.

4) Again, not clear if you are still talking about pin assignments or if you need help with timing constraints.  Check the Timing Analyzer user guide for the latter: https://www.intel.com/content/www/us/en/docs/programmable/683068.html

5) .sdc file is added to the Timing Analyzer settings in the Settings dialog box from the Assignments menu.  And as mentioned, pin assignments are automatically added to the .qsf file as you make them in the Pin Planner.

[RichardTanSY_Intel]

Do you need further help in regards to this case?

Regards,

Richard Tan

[ZhiqiangLiang]

@RichardTanSY_Intel 

Thank you!
Currently, no more questions as we are now debugging Cyclone10 on PCB.

Once the debugging is done, I may have further questions about avalon and axi4 lite

[RichardTanSY_Intel]

Glad to hear that. Thanks to @sstrell for helping to answer the latter part.

May I know if the debug process will take some time?

If it’s expected to take a while, I suggest we close this thread for now and open a new case to continue the discussion.

Does that sound good to you?

Regards,

Richard Tan

[ZhiqiangLiang]

@RichardTanSY_Intel 

The debugging will take place in 3 days.

[RichardTanSY_Intel]

Any update on this?

Regards,

Richard Tan