Stratix 10 FPGA Recalibration

[AnuragWho]

Hi, 

We are trying to implement JESD204B Interface between AFE7900 EVM (Transmitter) and Stratix 10 1SX280LU2F50E1VG EVM (Receiver).  To maintain JESD Link Stable, We need to Re-calibrate the FPGA.

The detailed Implementation process of Re-calibration which we tried is attached in the document.

We are not able to complete Re-calibration using the mentioned procedure. 

Kindly suggest correct procedure to perform the Re-calibration of the same.

[ZH_Intel]

Hi Anurag,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel

[AnuragWho]

Hi,

Can we have any update on the above query.

Regards

Anurag

[ZH_Intel]

Hi Anurag,

Apologize for the delayed response as we encounter technical difficulty.

Regarding to your question, you may refer to the JESD204B FPGA IP User guide under chapter 4.4. Clocking Scheme and 4.5. Reset Scheme, this chapter shows how to calibrate the transceiver, and steps to do it.

For more information refer below link:

1. JESD204B Intel® FPGA IP User Guide - 4.4.5. Transceiver Calibration Clock Source 
2. JESD204B Intel® FPGA IP User Guide - 4.5. Reset Scheme 

Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel

[ZH_Intel]

Hi Anurag,

Good day.

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you. 

Best Regards,

ZH_Intel