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DLync7
Novice
870 Views

Stratix 10 GX Dev Kit (L Tile) Programming Issues

Hi,

 

I am having trouble compiling .sof files to program the Dev kit.

 

I am able to use the BTS program and program provided .sof files using the BTS and Quartus programmer. However when I try to compile my own they fail on programming. The fail occurs at 12/13% every time and does not give me any error messages as to why it failed.

 

I am using Quartus 18.1. I'm trying to compile with projects in the examples folder from the FPGA Development Kit package (the production L tile package). I am also trying to create projects from scratch but I get the same result.

 

Are these provided projects for a different revision of the board? Or are the extra steps that need to be taken when using the example projects?

 

Thanks

 

2 Replies
DLync7
Novice
75 Views

As an update, I found some settings in a qsf file on the intel github page. Some key differences I think I have found are in the FPGA device numbers:

From Intel Github qsf:

#############################################################

# Device setup

#############################################################

set_global_assignment -name FAMILY "Stratix 10"

set_global_assignment -name DEVICE 1SG280LU3F50E3VG

 

From board package:

set_global_assignment -name FAMILY "Stratix 10"

set_global_assignment -name DEVICE 1SG280LU2F50E2VG

 

 

 

and in the VID settings:

 

From the Intel Github qsf:

#############################################################

# VID

#############################################################

set_global_assignment -name USE_PWRMGT_SCL SDM_IO14

set_global_assignment -name USE_PWRMGT_SDA SDM_IO11

set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"

set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"

set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677

set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F

set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00

set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON

set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY"

set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS

 

and from memory the board package had the same settings in the Quartus project but the slave device 0 address being either 55 or 5F.

 

Would these discrepancies be the cause of my compiling/programming issues? Is there any other settings other than pin assignments that need to be addressed before compiling the .sof files (no IP cores involved)?

 

 

 

DLync7
Novice
75 Views

Using the settings from the Intel Github resolved my issue

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