Stratix-10 SoC Dev kit- FMC loopback card frequency details

[HBhat2]

Hi,

We are using Stratix-10 SoC Dev kit and we are testing the Transceivers with the help of FMC loopback card received along with the kit. I see there are 2 transceiver clocks connected to REFCLK pin of FPGA XCVRs via FMC.

FMC pin (D4,D5) and (B20,B21) . These clocks are generated from Clock generator Si5330 present in the loopback card. I want to know what is the default frequency of clocks @ FMC pin (D4,D5) and (B20,B21).

With regards,

HPB

[AR_A_Intel]

Hello, Welcome to Intel Forum. I'm checking with support/board team regarding your issue. I'll be back with update.

[AR_A_Intel]

Sorry for the delay as I was out of office. Done some checking with team. Based on my understanding, FMC pin (D4,D5) and (B20,B21) is the input frequency source to the XCVR bank. So, there are no standard default frequency and it’s depended on the frequency that customer provide

[ZWU28]

hi,

I'm using a Cyclone 10 GX dev kit with FMC loopback card. I would like to know where I could find the schematic of the loopback card

[AR_A_Intel]

Can be found in PCB Schematic. See User Guide on how to determine PCB revision.https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-development-kit.html