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I have a Stratix III DSP kit which includes the HSMC Data Conversion card. I can run the "My first FPGA" design on the Stratix III board without issue, but when I connect the HSMC card to the Stratix III board and then try to program the FPGA with a design, I get the error: "Can't access JTAG chain".
I first discovered this error when trying to download the .sof for the DSP factory design stratixIII_3sl150_dsp_example_ChA. I also find that I get the same error if I try to run the "My first FGPA" again, even though that design worked fine before. I also discovered that I can get the "My first FGPA" to work if I remove the HSMC card or I disable the HSMA with the HSMA_BYPASS DIP switch (SW1). I have verified the jumper and switch settings indicated in the "DSP Developement Kit Getting Started Guide". Anyone have an idea what the problem might be? I'm a relative newcomer to FPGA and don't have a background in electrical engineering. ErinLink Copied
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So I ended up placing a service request with Altera, because after I made the previous post I was concerned there was something wrong with my Data Conversion HSMC card. They kindly responded that you do have to disable the JTAG chain at the HSMC port for this card, because there is no JTAG connection on it. So my Data Conversion card works fine; I just needed to enable the HSMA_BYPASS on SW1 (set to 1). As far as I can tell, the DSP kit User Guide says that the HSMA_BYPASS should be set to 0, so perhaps that is a typo in the Guide.
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--- Quote Start --- So my Data Conversion card works fine; I just needed to enable the HSMA_BYPASS on SW1 (set to 1). As far as I can tell, the DSP kit User Guide says that the HSMA_BYPASS should be set to 0, so perhaps that is a typo in the Guide. Erin --- Quote End --- I was confused by different versions of the DSP kit guide and now think I understand what are the desired positions for the SW1 on the Stratix III Dev board to use the HSMC card: FPGA_BYPASS = 1, HSMA_BYPASS = 0, HSMB_BYPASS = 0, MAX_ENABLE = 0. Those settings allow me to run the DSP example design discussed in the DSP Kit Getting Started User Guide. Those settings are consistent with the settings described on page 4-5, Table 4-2 of this guide: https://www.altera.co.jp/ja_jp/pdfs/literature/ug/ug_stratixiii_dsp_dev_kit.pdf, but are not consistent with Table A-2 on page A-1 of this guide: http://www.kanecomputing.co.uk/pdfs/altera%20dsp%20dev%20kit%20getting%20started%20user%20guidei.pdf So that's a good note to self to watch out for alternative versions of the guides. Erin
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