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FPGA Evaluation and Development Kits
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Stratix III Signal Level Problem

Honored Contributor II

One of our Stratix III Dev Kits has recently started playing up on some of its IO pins. We use a board connected to the HSMC connectors to drive external logic and some of these pins have started having trouble driving a logic 1 out.  


I disconnected the external board and generated an image that drives a pulsing signal out of each HSMC pin. Out of 160 pins between both ports I have 14 that do not drive out the full 0-2.5V range.  


12 of these are split between IO Banks 5A, 5C and 6A on the FPGA (3 from each) and they give me an output from roughly 0.1V (min) to 0.8V (max). 


The other 2 are on IO Bank 6A and give me 2.4V (min) to 2.6V (max). 


Anyone got any idea what could have happened to these pins and if there is anything I can do to fix this? 


I have tried bumping up the current strength to max which slightly improves the performance, but not by enough to give a solid '1' on my external interface. Also, I tried putting them through the ALTIO buf in the megawizard which made no difference whatsoever.
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