Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Honored Contributor I
1,121 Views

Stratix IV Dev Board with Nios II Ethernet Standard Design: No PHY connected

I have an Altera Stratix IV 4sgx230 Development Board and using the NIOS II Ethernet Standard Design Example. I have found an issue where the PHY communication fails with the error “No PHY connected” IF the default demo code has NOT been run which configures the PHY. A workaround is included, however I would like to know if others can replicate this problem or suggest what is wrong. I find it hard to believe Altera did not notice this. 

 

board: Altera 4sgx230 Development Board 

demo project instructions: using the nichestack tcp/ip stack – nios ii edition tutorial (https://www.altera.com/literature/tt/tt_nios2_tcpip.pdf

hardware design files: nios ii ethernet standard design example (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios...

software design files: Built from Simple Socket Server App/BSP template in Quartus 13.0 

quartus version: 13.0 

 

By default this design works. This means the dev board is powered on and initially runs its demo code loaded in flash which includes a simple socket server. I can then load the .sof and run the software from NIOS. Everything works – or appears that way. 

 

The issue occurs if you do NOT run the demo code from flash which configures the PHY. Easy way to do this is change the SW2 rotary switch from ‘0’ to ‘1’. Alternatively you can wipe the flash. When the board is powered on, no design is loaded to the FPGA. In this case, the PHY fails to communicate: 

 

 

 

InterNiche Portable TCP/IP, v3.1  

 

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  

prep_tse_mac 0 

Your Ethernet MAC address is 00:07:ed:ff:af:a0 

prepped 1 interface, initializing... 

[tse_mac_init] 

INFO : TSE MAC 0 found at address 0x0800a000 

ERROR : MAC Group[0] - No PHY connected! 

INFO : PCS[0.0] - Configuring PCS operating mode 

INFO : PCS[0.0] - PCS SGMII mode enabled 

ERROR : PHY[0.0] - No PHY connected! Speed = 100, Duplex = Full 

OK, x=0, CMD_CONFIG=0x00000000 

 

MAC post-initialization: CMD_CONFIG=0x04000203 

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created 

mctest init called 

IP address of et1 : 0.0.0.0 

Created "Inet main" task (Prio: 2) 

Created "clock tick" task (Prio: 3) 

DHCP timed out, going back to default IP address(es) 

 

Simple Socket Server starting up 

[sss_task] Simple Socket Server listening on port 30 

Created "simple socket server" task (Prio: 4) 

 

 

 

 

The error line is: “No PHY connected”. Ignore the later DHCP errors which is a side effect of the PHY communication failure. I believe the PHY is already configured when the default Altera demo is started from flash. When the default demo is disabled, the PHY fails to init. I suspect this may go unnoticed by most people. 

 

Can anyone recreate this problem or suggest any fixes? I am guessing the issue is in Qsys. I don’t think I’m going to spend the time to SignalTap the MDIO bus to the PHY. Instead, my solution is to abandon this demo project and instead use the triple speed ethernet design example (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios...). 

 

Any comments are welcome.
0 Kudos
2 Replies
Highlighted
Honored Contributor I
22 Views

The triple speed ethernet design example (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios...)has had some additional issues that I worked through. This post is simply to help others in case they run into the same problem.  

 

I initially switched to Quartus v14.0 and loaded the example project on Altera’s website specifically for 14.0: 4sgx230 triple speed ethernet zip file (14.0) (https://www.altera.com/content/dam/altera-www/global/en_us/others/support/examples/download/niosii-t...

 

While labeled as v14.0, this example project is clearly not generated from 14.0. Eclipse will fail to compile complaining of missing header files: bsp/drivers/src/altera_avalon_tse.h 

 

This is caused by the TSE driver is not included in the BSP because it is missing in Qsys. Opening the design in Qsys you will see the error: 

Component triple_speed_ethernet 13.0 not found or could not be instantiated 

 

This Qsys design although labeled as v14.0 was built with v13.0 components. Qsys is not compatible with older versions. 

 

The solution is to use the above design file labeled as v14.0 with Quartus v13.0.
0 Kudos
Highlighted
Honored Contributor I
22 Views

I am using the exact same board and configuration with Quartus II v15.0. As you said, driver for TSE is NOT included in the BSP. I was suggested in other forum (http://www.alteraforum.com/forum/showthread.php?t=50537)to change to QII v12.0 for things to work.  

 

This is ridiculous as my company has license for v15.0 and want to use other new features of QII v15.0. 

 

I get the following Nios II console message: 

 

InterNiche Portable TCP/IP, v3.1  

 

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  

prepped 0 interfaces, initializing... 

inet setup error: unable to find any working interfaces 

panic: IP 

dtrap - needs breakpoint
0 Kudos