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Honored Contributor I
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Stratix V Development Kit Transceiver Clock Settings

I'm new to FPGA and need to use the transceiver toolkit to transfer the data at rate from 5000MBps up to 10000MBps. After searching some information I download one sample project from <a href="http://www.alterawiki.com/wiki/Transceiver_Toolkit" target="_blank">http://www.alterawiki.com/wiki/Transceiver_Toolkit</a>, which is as follows:<br> 

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<a href="http://www.alterawiki.com/uploads/7/75/SV_7ch_11p3gbps.qar" target="_blank">http://www.alterawiki.com/uploads/7/75/SV_7ch_11p3gbps.qar</a><br> 

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<img src="http://www.alteraforum.com/forum/attachment.php?attachmentid=11723&amp;stc=1" border="0" alt=""><br> 

For this project, the Data rate by default is set as 11300MBps. While when I was trying changing it to some random value between 5000MBps and 10000MBps by using Qsys, some of the value cannnot be set. Even though some of the value is set successfully and can compile without any problem. But the thing is after I program it into the FPGA, the transceiver links cannot operate properly.<br> 

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Can I know what is the rule to adjust the base rate for this board?
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