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RJoy01
Beginner
285 Views

System hangs while testing Intel FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example User Guide example design

STRATIX 10DX DEC KIT

 

Here we have used Intel FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example User Guide example design for testing. when we tried to  run the DMA using Example Design Application the system got hanged. We are using QUARTUS PRO 19.4 version.

Test is performed ubuntu18.04LTS

TEST LOG(failed)

 

vvdn@vvdn-hp:~/Downloads/pcie_ed_software_18Feb2020_1955/software/user/example$ sudo ./intel_fpga_pcie_link_test

 

*********************************************************

Intel FPGA PCIe Link Test

Version 2.0

0: Automatically select a device

1: Manually select a device

*********************************************************

> 0

Opened a handle to BAR 0 of a device with BDF 0x100

 

*********************************************************

 0: Link test - 100 writes and reads

 1: Write memory space

 2: Read memory space

 3: Write configuration space

 4: Read configuration space

 5: Change BAR for PIO

 6: Change device

 7: Enable SRIOV

 8: Do a link test for every enabled virtual function

belonging to the current device

 9: Perform DMA

10: Quit program

*********************************************************

> 9

 

*********************************************************

Current DMA configurations

Run Read  (card->system)  ? 1

Run Write (system->card)  ? 1

Run Simultaneous      ? 1

Number of dwords/desc : 2048

Number of descriptors : 128

Total length of transfer  : 1024 KiB

*********************************************************

 0: Run DMA

 1: Toggle read DMA

 2: Toggle write DMA

 3: Toggle simultaneous DMA

 4: Set the number of dwords per descriptor

 5: Set the number of descriptors per DMA

 6: Return to main menu

*********************************************************

> 0

Enter the number of DMA operations to initiate; enter 0 for infinite loop:

>1

 

 

0 Kudos
12 Replies
SengKok_L_Intel
Moderator
109 Views

Hi,

 

Is the links test 100 read & write passed? Could you please reduce the number of descriptors per DMA, or number of Dwords per descriptor to see if this make any difference?

 

Regards -SK

RJoy01
Beginner
109 Views

No, the the link test failed .We are able to write to the bars but while we read the whole bar becomes fffffffffffff. After rebooting the host PC we are able to see the written data in the bar.

RJoy01
Beginner
109 Views

*********************************************************

Intel FPGA PCIe Link Test

Version 2.0

0: Automatically select a device

1: Manually select a device

*********************************************************

> 0

Opened a handle to BAR 0 of a device with BDF 0x100

 

*********************************************************

 0: Link test - 100 writes and reads

 1: Write memory space

 2: Read memory space

 3: Write configuration space

 4: Read configuration space

 5: Change BAR for PIO

 6: Change device

 7: Enable SRIOV

 8: Do a link test for every enabled virtual function

belonging to the current device

 9: Perform DMA

10: Quit program

*********************************************************

> 5

Changing BAR...

Enter BAR number (-1 for none):

> 2

Successfully changed BAR!

 

*********************************************************

 0: Link test - 100 writes and reads

 1: Write memory space

 2: Read memory space

 3: Write configuration space

 4: Read configuration space

 5: Change BAR for PIO

 6: Change device

 7: Enable SRIOV

 8: Do a link test for every enabled virtual function

belonging to the current device

 9: Perform DMA

10: Quit program

*********************************************************

> 2

Enter address to read, in hex:

> 0x4

Reading from BDF 0x100 BAR 0x2 offset 0x4..

Read 0

 

*********************************************************

 0: Link test - 100 writes and reads

 1: Write memory space

 2: Read memory space

 3: Write configuration space

 4: Read configuration space

 5: Change BAR for PIO

 6: Change device

 7: Enable SRIOV

 8: Do a link test for every enabled virtual function

belonging to the current device

 9: Perform DMA

10: Quit program

*********************************************************

> 1

Enter address to write, in hex:

> 0x4

Enter 32-bit data to write, in hex:

> 0xaabb

Writing 0xaabb at BDF 0x100 BAR 0x2 offset 0x4..

Wrote successfully!

 

*********************************************************

 0: Link test - 100 writes and reads

 1: Write memory space

 2: Read memory space

 3: Write configuration space

 4: Read configuration space

 5: Change BAR for PIO

 6: Change device

 7: Enable SRIOV

 8: Do a link test for every enabled virtual function

belonging to the current device

 9: Perform DMA

10: Quit program

*********************************************************

> 2

Enter address to read, in hex:

> 0x4

Reading from BDF 0x100 BAR 0x2 offset 0x4..

Read 0xffffffff

 

*********************************************************

 0: Link test - 100 writes and reads

 1: Write memory space

 2: Read memory space

 3: Write configuration space

 4: Read configuration space

 5: Change BAR for PIO

 6: Change device

 7: Enable SRIOV

 8: Do a link test for every enabled virtual function

belonging to the current device

 9: Perform DMA

10: Quit program

*********************************************************

> 10

 

 

 

 

 

 

 

 

AFTER REBOOT

 

vvdn@vvdn-hp:~$ sudo md.l f0210004

f0210004: 0000aabb 00000000 00000000 00000000 ................

f0210014: 00000000 00000000 00000000 00000000 ................

f0210024: 00000000 00000000 00000000 00000000 ................

f0210034: 00000000 00000000 00000000 00000000 ................

f0210044: 00000000 00000000 00000000 00000000 ................

f0210054: 00000000 00000000 00000000 00000000 ................

f0210064: 00000000 00000000 00000000 00000000 ................

f0210074: 00000000 00000000 00000000 00000000 ................

f0210084: 00000000 00000000 00000000 00000000 ................

f0210094: 00000000 00000000 00000000 00000000 ................

f02100a4: 00000000 00000000 00000000 00000000 ................

f02100b4: 00000000 00000000 00000000 00000000 ................

f02100c4: 00000000 00000000 00000000 00000000 ................

f02100d4: 00000000 00000000 00000000 00000000 ................

f02100e4: 00000000 00000000 00000000 00000000 ................

f02100f4: 00000000 00000000 00000000 00000000 ................

 

RJoy01
Beginner
109 Views

SengKok_L_Intel
Moderator
109 Views

Hi,

 

I tested v19.4 design example, and I've encountered the same problem as you reported here. Therefore, I will feedback it to the Intel PSG engineering team to resolve the problem. For the moment, I attached the v19.3 sof file for you to perform a quick test, it can run the DMA test without hang, where the link test and memory read/write test are actually not supported here.

 

Regards -SK 

RJoy01
Beginner
109 Views

Thanks

By using the SOF file you shared ,DMA operation work properly when i reduce the descriptor count

SengKok_L_Intel
Moderator
109 Views

​Please download the v19.3 sof file here.

SengKok_L_Intel
Moderator
109 Views

This is glad to know that. Please use v19.3 as the workaround.

 

Regards -SK

SengKok_L_Intel
Moderator
109 Views

For your information, this issue is tentatively targeted to fix in the next version of the Quartus software version release.

SengKok_L_Intel
Moderator
109 Views

Hi Romy Joy,

 

A quick check, is the 19.3 image also working for Memory Read/Write test when changing the BAR# to 2?

 

Regards -SK

RJoy01
Beginner
109 Views

yes with this image i am able to perform memory read/ write in bar 2

 

SengKok_L_Intel
Moderator
109 Views

Thanks for the confirmation. Please use v19.3 as a workaround, and this issue will be fixed in the next software version release.

 

Regards -SK

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