issue in detail
I am trying to implement Altera PFL IP (configuration is done for FPPx16) in MAX5 CPLD,when I am doing the timing analysis ,the timing report shows there is negative slack related to PFL_CLK.PFL_CLK frequency is set to 100MHz and it is genenrated using an external Oscillator.
In the PFL GUI,I chose area optimization.The flash Programming IP FIFO size is 16 words. My requirement is to work the design at 100MHz.
From the CPLD design compilation reports,the Fmax is shown only 62.36MHz.The CPLD design contains only this PFL_mega(Altera IP) function.The Total logic elements utilization is 57% only.
I have a few questions,
1. what is the max frequency the altera pfl mega function can support?
2. Is there any other optimization techiniques possible with the Quartus II 13.1.
optimization options which I tried,
1. speed instead of area then the compilation failed due to lack of resources.
2. performed Register re-timing by checking the option in physical synthesis optimizations
but after performing the above optimization options no .2,the result was the same as above. I would appreciate any help to circumvent the issue.
Thanks in advance....