Transceivers

[Madhuri1]

Hello

I want to implement transceivers on SRATIX V FPGA, I have gone through the IP, there are many, but i found custom PHY transceiver IP suitable for my application, I want to operate Serdes @ 2Gbps. There is this interface called phy_mgmt (PHY management). I have gone through some example designs, where in they are using NIOS II processor for control and command. and processor in the picture, for me is very confusing, and creating block diagram seems very difficult, even i insert an already generated IP, i am not able to see in the workspace of block diagram creator. Is it possible to configure transceivers with our custom data, without the intervention of processor, i want to give the Rx/Tx on SMA only.

Regards,
Madhuri

[WZ2]

Hi there,

Of course, it’s definitely possible. The Nios II processor in those examples is simply acting as a master to issue commands to the transceiver IP. You can absolutely replace it with your own custom logic to control and configure the IP as needed.

Best regards,

WZ

[WZ2]

Hi there,

Of course, it’s definitely possible. The Nios II processor in those examples is simply acting as a master to issue commands to the transceiver IP. You can absolutely replace it with your own custom logic to control and configure the IP as needed.

Best regards,

WZ

[WZ2]

Hi there,

Of course, it’s definitely possible. The Nios II processor in those examples is simply acting as a master to issue commands to the transceiver IP. You can absolutely replace it with your own custom logic to control and configure the IP as needed.

Best regards,

WZ