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JhonatanRubin
Beginner
176 Views

Tri Speed ETH MAC - MAX10

Hi all, We are using CAST UDP IP core on MAX 10, as part of the design it uses the TriSpeed ETH MAC, the final HW design is fimiliar to the MAX10 EVB (10M50DAF484C6GES with RGMII to Marvell 88e1111) At first stage we loaded to design to the MAX10 EVB and everthing works perfect, we get link, ping command, arp and full UDP data transfer functionality At the secod stage we used our custom board with a 10M16DAF484I7G, a short harnees with RGMII signals to an EVB which we have removed the MAX10 in order to use it as an host card for the marvell phy (the final custom board will hold both the MAX10 and the phy on the same PCB) The main diffrence except the RGMII harness routing is that the first stage (all in the EVB) uses a 2.5V RGMII whereas the second stage uses a 3.3V RGMII The results on the second stage weren't good, we goot the green LED on (Link from the phy towards the PC) but the orange LED didnt turned on I suspect the TRI Speed ETH MAC might require a 2.5V bank, can someone approve? is it possible to work with a 3.3V bank? except than the problamtic RGMII harness can anyone point any other problematic issues? Thanks in advance Jhonatan

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4 Replies
SengKok_L_Intel
Moderator
169 Views

This may be due to the IO buffer performance instead of related TSE IP related. It is expected that the 3.3V IO performance is lower than the 2.5V as the 3.3V is a target for low-speed application with the wide threshold requirement but causing a slow rise/hold time. Also, did you change the VCCIO on board when you switch the IO from 2.5 to 3.3V? This also might impact the IO behavior.

 

Regards -SK 


JhonatanRubin
Beginner
155 Views

Hi SengKok_L_Intel Thank you very much for the replay, I always use the same IO standard as connected to the Vccio, therfore when i used the bank as a 3.3V it is because the Vccio is 3.3V, is it possible to connect a 3.3V rail to the Vccio and a 2.5V IO stadnard? As for the differences between the IO performance, i didnt found any documentation that state what you are saying, the only thing i found is a "high speed" decleration regardless of what Voltage is used, can you refer any documentation that backs up the performance differences according to the IO stadnard? Thanks Jhonatan
SengKok_L_Intel
Moderator
149 Views

Hi


Theoretically 3.3V IO standard is slower if compare with other buffer.


As per MAX10 datasheet, this is suggested to perform IBIS simulation based on your specific design and system setup to determine the maximum achievable frequency in your system. Please ensure proper timing closer in your design as it may impact the performance.


https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf...


Regards -SK


SengKok_L_Intel
Moderator
128 Views

Hi,


If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


Regards -SK


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