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True Dual Port RAM with write and read to addr_a and read from addr_b in the same cycle

ASoko19
Novice
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Hi.

 

I'm currently working on RAM based Tightly Coupled Memory (TCM) with instruction read and data write and read (to the same address) in the same cycle. Below you can find my RTL:

//------------------------------------------------------------------------------- // Local signal declaration //------------------------------------------------------------------------------- (* ramstyle = "M9K, M10K" *) logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1]; logic [3:0] wenbb; //------------------------------------------------------------------------------- // Port B memory behavioral description //------------------------------------------------------------------------------- assign wenbb = {4{wenb}} & webb; always_ff @(posedge clk) begin if (wenb) begin if (wenbb[0]) begin memory_array[addrb][0] <= datab[0+:8]; end if (wenbb[1]) begin memory_array[addrb][1] <= datab[8+:8]; end if (wenbb[2]) begin memory_array[addrb][2] <= datab[16+:8]; end if (wenbb[3]) begin memory_array[addrb][3] <= datab[24+:8]; end end qb <= memory_array[addrb]; end //------------------------------------------------------------------------------- // Port A memory behavioral description //------------------------------------------------------------------------------- always_ff @(posedge clk) begin qa <= memory_array[addra]; end

In Embedded Memory User Guide it states, that TDP RAM can perform only 2 simultaneous operations per clock.

However, synthesis results for MAX10 show, that my TCM is implemented using only 1 memory array. Thus, I have 3 simultaneous operations in one cycle.

For Arria V the same code results in 2 memory arrays.

So, I have the following question:

Why doesn't my TCM code result in 2 memory arrays for MAX10?

 

Any help would be appreciated.

Thanks in advance.

BR,

Sokolov Artem

 

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