FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6027 Discussions

Warning (332043): Overwriting existing clock: ddr3b_dqs_p[5]_OUT



I am using NIOS ii ethernet main system example design (https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/nios-ii-simple-socket-server-ethernet-example-for-cvgt/  )

I have integrated my RTL with the provided example design in qsys. I am using Avalon interface in my design. I am planning to run Avalon part of my code at 100 MHz.

The SDRAM controller IP uses ref clock of 125 MHz to generate AFI clock of 150 MHz. I have not connected the AFI clock (afi_clk) and AFI reset to any IP in qsys. Although I supply the input clock from a clock source to my RTL IP.

I generated the design and gave for compilation. I have contrained the clock for 50 MHz, yet the timing always fails. The failing path shown is sdram pll always. 

Moreover. I get the warnings like:

Warning (332043): Overwriting existing clock: altera_reserved_tck
Warning (332043): Overwriting existing clock: clkin_125
Warning (332043): Overwriting existing clock: eth_std_main_system_inst|sdram|eth_std_main_system_sdram_p0_sampling_clock
Warning (332043): Overwriting existing clock: ddr3b_clk_p
Warning (332043): Overwriting existing clock: ddr3b_clk_n

The detailed warnings are provided in the attachment below. The warnings were not there when i compiled the nios example design separately.

1) I would like to understand what these warnings are?

2) Are they serious or ignorable? How to remove these?

3) Should I connect the sdram AFI clock to my module that runs Avalon? (I have attached qsys image )

3) The timing failing path is sdram PLL, what can i do about it?


Thanks in advance.




0 Kudos
1 Reply

Hi Susmita,

First of all, thanks for reaching us.

Please refer to this KDB and let me know any questions you may have.





0 Kudos