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We have our Cyclone10GX custom PCB, which is having cy10 interfaced to SFP module(1.25Gpbs Finisar) via its transceiver port. How to prove that the board is fine wrt Signal integrity.

RGula
Beginner
472 Views

We have tested the board using transceiver toolchain( avilable in Quartus) using a project with NATIVE-PHY ip integrated.

The transceiver toolchain shows BER of zero when we test at data rate of 1250Mbps(when we do external loopback using optical patch cord)

Does this prove that our board is fine wrt signal integrity??

Or we need to integrate TSE-MAC ip in our project and then we can conclude the board signal integrity??

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3 Replies
Crisselle_Intel
Moderator
248 Views

Hello RGula,

 

Thank you for posting in Intel Ethernet Communities. 

 

Your query will be best answered by our FPGA Support team, we will help you to move this post to the designated team. Please feel free to contact us if you need any assistance from Ethernet support team.

 

Best regards,

Crisselle C

Intel Customer Support

A Contingent Worker at Intel

Deshi_Intel
Moderator
247 Views

Hi,

 

The main factor that will affect your board signal integrity from your Quartus design is the transceiver PHY PMA setting.

  • As long as you are still using same PMA setting then the rest of design logic doesn't matter that much. (for instance, whether you add in MAC IP or not)
  • However, if you change PMA setting then you would need to retest your board signal integrity again.

 

Typically we would advise to hit at least 95% BER confidence level to guarantee good signal integrity performance. However, this is just general guideline and different protocol may have its own spec to meet.

 

Feel free to checkout below BER confidence level calculator link

 

Thanks.

 

Regards,

dlim

 

 

TRAN_HIEU_007
New Contributor I
191 Views

Hi RGula can you share me (quartus project test) Cyclone 10GX interface SFP module. Thank! My mail is: hieu.tranthe@gmail.com

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