FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5931 Discussions

What is the overshoot and undershoot values for the LVDS logic of 2.5V

VKuma63
Beginner
‎06-19-2019 10:58 AM
1,123 Views

In my design i am using the cyclone 3 device with the manufacturer part number "EP3C55F484I7NGA". I was doing SI simulations for the 2.5V nets. In the device datasheet they have not given the electrical specification of the maximum overshoot and undershoot values.

 

Kindly provide, what can be considered as overshoot and undershoot for 2.5V LVDS logic.

0 Kudos

Link Copied

2 Replies
YuanLi_S_Intel
Employee
‎06-20-2019 02:09 AM
831 Views

Why not? Please refer to link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf (Page 2)

0 Kudos
Copy link
YuanLi_S_Intel
Employee
‎06-20-2019 02:12 AM
831 Views

Overshoot and undershoot is not depending on the I/O Standard. Is actually depending on the I/O buffer. Thus, you may refer to the link as stated above. For LVDS, what you need to consider is the VICM and VID.

 

Regards,

YL

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.