Using the Quartus Prime software during the analysis and sythesis stage, we get compilation issues due to undefined text macros. The text macros are declared in their own file and used in other files of our design. The file is included in the project and looks to be analyzed before the other files which use the macros, yet there are still errors saying undefined text macro.
We recommend user to just add the `include "define.v" statement to the start of your design file and add macro file in file list.
Hope it helps! Let me know if you need any further assistance.
Yes, We can use by including the macro files into the file list. If we don't include macro files in file list than we have to `include <file> in each Verilog module.
Please check the attached image.