FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6211 Discussions

Where Can I find the Timing Diagram of Avalon-MM Interface in Arria10 EMIF IP Core?

SYiwe
Novice
‎04-11-2019 02:29 AM
658 Views

 

Hi,

I'm using EMIF IP Core in my Arria10 SoC, there's an auto-generated Avalon-MM interface to communicate with user logic, but I haven't found the timing diagram of Avalon-MM in the EMIF user guide so far, where can I find the the correct timing diagram?

Besides, how can I confirm the relationship between the Avalon-MM's address and external-memory's address?

Thanks, regards.

0 Kudos

Link Copied

1 Reply
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.