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Can someone help me?
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Hi Shirley
Is it possible that you share the full terminal logs?
This is to see which stage the board have already booted.
Regards
Jingyang, Teh
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Of course, the complete log is in the attachment pack above named "uboot output info.txt", it stucks at the stage of u-boot SPL...
This is the result that I packaged the logic bitstream and uboot-spl.hex into a new sof and burning the board in.
And I noticed the DRAM size is different with the demo project, then I refer to this post to make modifications. But it still fails to boot...
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Hi
Could you try changing the parameter of the "CONFIG_NR_DRAM_BANKS" back to the default and try again?
CONFIG_NR_DRAM_BANKS=2
Regards,
Jingyang, Teh
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Hi
Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.
Regards
Jingyang, Teh
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The problem is solved, it is the SDRAM clock configuration problem of the fpga, just refer to the manual configuration and it will work normally.

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