FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5203 Discussions

clarification in virtual jtag communication

AGlad5
Beginner
258 Views

We have made a design with a virtual jtag instance for a Stratix 10 FPGA. While performing virtual dr shifts we have been seeing unexpected instant feeback behavoir. It seems as though the dr shift instantly comes back to me with four less bits of data when my design should be sending me completely unrelated data of that which I sent in. Has anyone else experienced this or might know what is going on?

0 Kudos
1 Reply
ShafiqY_Intel
Employee
204 Views

Hi AGlad5,

 

It has been a while since you have posted an update to this Case. Do you have any latest update? 

Can I say this issue is no longer an issue now?

 

Thanks.

 

Regards,

Matt

Regards,

Reply