We have made a design with a virtual jtag instance for a Stratix 10 FPGA. While performing virtual dr shifts we have been seeing unexpected instant feeback behavoir. It seems as though the dr shift instantly comes back to me with four less bits of data when my design should be sending me completely unrelated data of that which I sent in. Has anyone else experienced this or might know what is going on?
It has been a while since you have posted an update to this Case. Do you have any latest update?
Can I say this issue is no longer an issue now?