FPGA, SoC, And CPLD Boards And Kits
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clock duty of the output of altlvds tx

Lambert
New Contributor I
248 Views

Hi everyone,

I want to know one thing that when I want to use altlvds tx to transimit 0->1->0 to make clock, I got the clock , its duty is not 50% no matter what the frequency, I don't know the matter, can anyone help me? The waveform of the clock is like below fig.clk_eye.jpg

B.S.

Lambert

 

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Rahul_S_Intel1
Employee
101 Views

Hi ,

Can you check the losses in the board and try to see the simulation , and compare the board level simulation ( IBIS ) with actual result

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