In a 5CEA9 design， first power up VCC， and then VCCPD & VCCIO in all IO banks are not powered up right now, but at sometime later in tens of minutes，what will happen to the FPGA device? Will the FPGA device be damaged ?
Are you using same regulator for VCCPD and VCCIO ?
Please check AN662, Power Management in Cyclone V Devices & Cyclone V Devices handbook for POR requirement.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Thanks for your reply, Anand,
The reason that I do this is to lower the power consumption of the FPGA device when the FPGA is not needed to work. So I want to shut some power rail but at the same time the FPGA should keep the configuration correctly.
I will check AN662 carefully.